Datasheet

Low Voltage Inhibit (LVI)
MC68HC908JL3E Family Data Sheet, Rev. 4
128 Freescale Semiconductor
14.4 LVI Control Register (CONFIG2/CONFIG1)
The LVI module is controlled by three bits in the configuration registers, CONFIG1 and CONFIG2.
LVID — Low Voltage Inhibit Disable Bit
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
LVIT1, LVIT0 — LVI Trip Voltage Selection
These two bits determine at which level of V
DD
the LVI module will come into action. LVIT1 and LVIT0
are cleared by a Power-On Reset only.
14.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power-consumption standby modes.
14.5.1 Wait Mode
The LVI module, when enabled, will continue to operate in WAIT Mode.
14.5.2 Stop Mode
The LVI module, when enabled, will continue to operate in STOP Mode.
Address: $001E
Bit 7654321Bit 0
Read:
IRQPUDRRLVIT1LVIT0RRR
Write:
Reset:000
Not affected Not affected
000
POR:00000000
R=Reserved
Figure 14-2. Configuration Register 2 (CONFIG2)
Address: $001F
Bit 7654321Bit 0
Read:
COPRS R R LVID R SSREC STOP COPD
Write:
Reset:00000000
R=Reserved
Figure 14-3. Configuration Register 1 (CONFIG1)
LVIT1 LVIT0
Trip Voltage
(1)
1. See Chapter 16 Electrical Specifications for full parameters.
Comments
00V
LVR 3
(2.4V) For V
DD
=3V operation
01V
LVR3
(2.4V) For V
DD
=3V operation
10V
LVR 5
(4.0V) For V
DD
=5V operation
11 Reserved