Datasheet

Break Module (BREAK)
MC68HC908JL3E Family Data Sheet, Rev. 4
130 Freescale Semiconductor
15.3.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. (See 5.7.3 Break Flag Control Register (BFCR) and see the Break Interrupts
subsection for each module.)
15.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD
($FEFC:$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
15.3.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
15.3.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V
TST
is present on the RST pin.
Addr.Register Name Bit 7654321Bit 0
$FE00
Break Status Register
(BSR)
Read:
RRRRRR
SBSW
R
Write: See note
Reset: 0
$FE03
Break Flag Control
Register
(BFCR)
Read:
BCFERRRRRRR
Write:
Reset: 0
$FE0C
Break Address High
Register
(BRKH)
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset:00000000
$FE0D
Break Address low
Register
(BRKL)
Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset:00000000
$FE0E
Break Status and Control
Register
(BRKSCR)
Read:
BRKE BRKA
000000
Write:
Reset:00000000
Note: Writing a 0 clears SBSW.
= Unimplemented R = Reserved
Figure 15-2. Break I/O Register Summary