Datasheet

Monitor ROM
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor 25
$0027
TIM Channel 0 Register Low
(TCH0L)
Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset: Indeterminate after reset
$0028
TIM Channel 1 Status and
Control Register (TSC1)
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
$0029
TIM Channel 1 Register High
(TCH1H)
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset: Indeterminate after reset
$002A
TIM Channel 1 Register Low
(TCH1L)
Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset: Indeterminate after reset
$002B
↓
$003B
Unimplemented
Read:
Write:
$003C
ADC Status and Control
Register (ADSCR)
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write:
Reset:00011111
$003D
ADC Data Register
(ADR)
Read:AD7AD6AD5AD4AD3AD2AD1AD0
Write:
Reset: Indeterminate after reset
$003E
ADC Input Clock Register
(ADICLK)
Read:
ADIV2 ADIV1 ADIV0
00000
Write:
Reset:00000000
$003F
Unimplemented
Read:
Write:
$FE00
Break Status Register
(BSR)
Read:
RRRRRR
SBSW
R
Write: See note
Reset: 0
Note: Writing a 0 clears SBSW.
$FE01
Reset Status Register
(RSR)
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR:10000000
$FE02 Reserved
Read:
RRRRRRRR
Write:
$FE03
Break Flag Control
Register (BFCR)
Read:
BCFERRRRRRR
Write:
Reset: 0
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 4)