Datasheet

System Integration Module (SIM)
MC68HC908JL3E Family Data Sheet, Rev. 4
50 Freescale Semiconductor
Figure 5-1. SIM Block Diagram
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
$FE00
Break Status Register
(BSR)
Read:
RRRRRR
SBSW
R
Write: NOTE
Reset:00000000
Note: Writing a 0 clears SBSW.
$FE01
Reset Status Register
(RSR)
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR:10000000
$FE02 Reserved
Read:
RRRRRRRR
Write:
Reset:
$FE03
Break Flag Control
Register (BFCR)
Read:
BCFERRRRRRR
Write:
Reset: 0
= Unimplemented R = Reserved
Figure 5-2. SIM I/O Register Summary
STOP/WAIT
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERRUPT CONTROL
AND PRIORITY DECODE
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
OSCOUT (FROM OSCILLATOR)
INTERNAL CLOCKS
MASTER
RESET
CONTROL
RESET
PIN LOGIC
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
RESET
CONTROL
SIM
COUNTER
COP CLOCK
2OSCOUT (FROM OSCILLATOR)
÷2
USB RESET (FROM USB MODULE)
V
DD
INTERNAL
PULL-UP