MC68HC908JL3/JK3E/JK1E MC68HRC908JL3/JK3E/JK1E MC68HLC908JL3/JK3E/JK1E MC68HC903KL3E/KK3E MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E Data Sheet M68HC08 Microcontrollers MC68HC908JL3E Rev. 4 10/2006 freescale.
MC68HC908JL3/JK3E/JK1E MC68HRC908JL3/JK3E/JK1E MC68HLC908JL3/JK3E/JK1E MC68HC908KL3E/KK3E MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date October 2006 Nov 2004 Dec 2002 May 2002 Revision Level Page Number(s) Description Table 4-1. Instruction Set Summary — Updated table to include the WAIT instruction. 42 5.7.1 Break Status Register (BSR) — Updated for clarity. 63 5.7.2 Reset Status Register (RSR) — Updated description for clarity.
List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 3 Configuration Registers (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Chapters MC68HC908JL3E Family Data Sheet, Rev.
Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . .
Table of Contents 4.3.4 4.3.5 4.4 4.5 4.5.1 4.5.2 4.6 4.7 4.8 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . .
Chapter 6 Oscillator (OSC) 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.5 6.5.1 6.5.2 6.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-tal Oscillator (MC68HC908JL3E/JK3E/JK1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC Oscillator (MC68HRC908JL3E/JK3E/JK1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . .
Table of Contents 8.5 8.6 8.6.1 8.6.2 8.7 8.8 8.9 8.9.1 8.9.2 8.9.3 8.9.4 8.9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . .
10.4 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.3 Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Chapter 14 Low Voltage Inhibit (LVI) 14.1 14.2 14.3 14.4 14.5 14.5.1 14.5.
16.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 16.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Chapter 17 Mechanical Specifications 17.1 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Package Dimensions . . . . . . . . .
Table of Contents Appendix C MC68HC908KL3E/KK3E C.1 C.2 C.3 C.4 C.5 C.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Registers . . . . . . . .
Chapter 1 General Description 1.1 Introduction The MC68H(R)C908JL3E is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. A list of MC68H(R)C908JL3E device variations is shown in Table 1-1. Table 1-1.
General Description 1.
MCU Block Diagram 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68H(R)C908JL3E.
General Description 1.4 Pin Assignments IRQ 1 28 RST PTA0/KBI0 2 27 PTA5/KBI5 VSS 3 26 PTD4/TCH0 OSC1 4 25 PTD5/TCH1 OSC2/RCCLK/PTA6/KBI 5 24 PTD2/ADC9 PTA1/KBI1 6 23 PTA4/KBI4 VDD 7 22 PTD3/ADC8 PTA2/KBI2 8 21 PTB0/ADC0 PTA3/KBI3 9 20 PTB1/ADC1 PTB7/ADC7 10 19 PTD1/ADC10 PTB6/ADC6 11 18 PTB2/ADC2 PTB5/ADC5 12 17 PTB3/ADC3 PTD7 13 16 PTD0/ADC11 PTD6 14 15 PTB4/ADC4 MC68H(R)C908JL3E Figure 1-2.
NC VSS PTA0/KBI0 IRQ RST PTA5/KBI5 PTD4/TCH0 PTD5/TCH1 NC 46 45 44 43 42 41 40 39 38 37 NC NC 47 48 NC Pin Assignments 36 NC NC 1 NC 2 35 NC OSC1 3 34 NC OSC2/RCCLK/PTA6/KBI6 4 33 PTD2/ADC9 PTA1/KBI1 5 32 PTA4/KBI4 NC 6 31 PTD3/ADC8 MC68H(R)C908JL3E 25 NC NC 24 NC 13 NC 12 23 NC NC 26 22 11 PTB2/ADC2 NC 21 PTD1/ADC10 PTB3/ADC3 27 20 10 PTD0/ADC11 PTB7/ADC7 19 PTB1/ADC1 PTB4/ADC4 28 18 9 PTD6 PTA3KBI3 17 PTB0/ADC0 PTD7 29 16 8 PTB5/A
General Description 1.5 Pin Functions Description of the pin functions are provided in Table 1-2. Table 1-2. Pin Functions PIN NAME VDDJL3JL3 PIN DESCRIPTION IN/OUT VOLTAGE LEVEL In 5V or 3V Out 0V Power supply. VSS Power supply ground RST RESET input, active low. With Internal pull-up and Schmitt trigger input. Input VDD to VTST IRQ External IRQ pin. With software programmable internal pull-up and schmitt trigger input. This pin is also used for mode entry selection.
Chapter 2 Memory 2.1 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: • 4,096 bytes of user Flash — MC68H(R)C908JL3E/JK3E 1,536 bytes of user Flash — MC68H(R)C908JK1E • 128 bytes of RAM • 48 bytes of user-defined vectors • 960 bytes of Monitor ROM 2.2 I/O Section Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers.
Memory $0000 ↓ $003F I/O REGISTERS 64 BYTES $0040 ↓ $007F RESERVED 64 BYTES $0080 ↓ $00FF RAM 128 BYTES $0100 ↓ $EBFF UNIMPLEMENTED 60,160 BYTES $EC00 ↓ $FBFF FLASH MEMORY MC68H(R)C908JL3E/JK3E 4,096 BYTES $FC00 ↓ $FDFF MONITOR ROM 512 BYTES $FE00 BREAK STATUS REGISTER (BSR) $FE01 RESET STATUS REGISTER (RSR) $FE02 RESERVED (UBAR) $FE03 BREAK FLAG CONTROL REGISTER (BFCR) $FE04 INTERRUPT STATUS REGISTER 1 (INT1) $FE05 INTERRUPT STATUS REGISTER 2 (INT2) $FE06 INTERRUPT STATUS REGISTER
Monitor ROM Addr.
Memory Addr.
Monitor ROM Addr.
Memory Addr.
Random-Access Memory (RAM) Table 2-1.
Memory During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. 2.5 Flash Memory This sub-section describes the operation of the embedded Flash memory. The Flash memory can be read, programmed, and erased from a single external supply.
Flash Control Register 2.7 Flash Control Register The Flash Control Register controls Flash program and erase operations. Address: Read: $FE08 Bit 7 6 5 4 0 0 0 0 0 0 0 Write: Reset: 0 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 = Unimplemented Figure 2-4. Flash Control Register (FLCR) HVEN — High Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation.
Memory 2.8 Flash Page Erase Operation Use the following procedure to erase a page of Flash memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80 or $XXC0. The 48-byte user interrupt vectors area also forms a page. Any page within the 4K bytes user memory area ($EC00–$FBFF) can be erased alone. The 48-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. Mass erase is required to erase this page. 1.
Flash Program Operation 2.10 Flash Program Operation Programming of the Flash memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this step-by-step procedure to program a row of Flash memory (Figure 2-5 shows a flowchart of the programming algorithm): 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2.
Memory 1 Set PGM bit Algorithm for programming a row (32 bytes) of Flash memory 2 Write any data to any Flash address within the row address range desired 3 Wait for a time, tnvs 4 Set HVEN bit 5 Wait for a time, tpgs 6 7 Write data to the Flash address to be programmed Wait for a time, tPROG Completed programming this row? Y N NOTE: The time between each Flash address change (step 6 to step 6), or the time between the last Flash address programmed to clearing PGM bit (step 6 to step 9) mu
Flash Block Protect Register 2.12 Flash Block Protect Register The Flash Block Protect Register is implemented as an 8-bit I/O register. The value in this register determines the starting address of the protected range within the Flash memory. Address: Read: Write: Reset: $FE09 Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 0 0 0 0 0 0 0 0 Figure 2-6.
Memory MC68HC908JL3E Family Data Sheet, Rev.
Chapter 3 Configuration Registers (CONFIG) 3.1 Introduction This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers enables or disables the following options: • Stop mode recovery time (32 × 2OSCOUT cycles or 4096 × 2OSCOUT cycles) • STOP instruction • Computer operating properly module (COP) • COP reset period (COPRS), 8176 × 2OSCOUT or 262,128 × 2OSCOUT • Enable LVI circuit • Select LVI trip voltage 3.
Configuration Registers (CONFIG) LVID — Low Voltage Inhibit Disable Bit 1 = Low Voltage Inhibit disabled 0 = Low Voltage Inhibit enabled SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 × 2OSCOUT cycles instead of a 4096 × 2OSCOUT cycle delay. 1 = Stop mode recovery after 32 × 2OSCOUT cycles 0 = Stop mode recovery after 4096 × 2OSCOUT cycles NOTE Exiting stop mode by pulling reset will result in the long stop recovery.
Chapter 4 Central Processor Unit (CPU) 4.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 4.
Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 4-1. CPU Registers 4.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
CPU Registers 4.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
Central Processor Unit (CPU) 4.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 4-6.
Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
Central Processor Unit (CPU) 4.7 Instruction Set Summary Table 4-1 provides a summary of the M68HC08 instruction set.
Instruction Set Summary V H I N Z C BHS rel Branch if Higher or Same (Same as BCC) BIH rel BIL rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 (A) & (M) BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Tabl
Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Clear Compare A with M Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A Decrement DIV Divide INC opr INCA INCX INC opr,X INC ,X INC opr,SP Exclusive OR M with A Increment DIR INH INH 0 – – 0 1 – INH IX1 IX SP1
Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine LDHX #opr LDHX opr Load H:X from M 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT – – – – – – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A ← (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 H:
Central Processor Unit (CPU) V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 4-1.
Opcode Map SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte – – 1 – – – INH 83 9 CCR ← (A) INH 84 2 X ← (A) – – – – – – INH 97 1 A ← (CCR) – – – – – – INH 85 (A) – $00 or (X) – $00 or (M) – $00 DIR INH INH 0 – – – IX1 IX SP1 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH
MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
Chapter 5 System Integration Module (SIM) 5.1 Introduction This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 5-1. Figure 5-2 is a summary of the SIM I/O registers. The SIM is a system state controller that coordinates CPU and exception timing.
System Integration Module (SIM) MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK 2OSCOUT (FROM OSCILLATOR) OSCOUT (FROM OSCILLATOR) ÷2 VDD CLOCK CONTROL INTERNAL PULL-UP RESET PIN LOGIC INTERNAL CLOCKS CLOCK GENERATORS POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) USB RESET (FROM USB MODUL
SIM Bus Clock Control and Generation Addr. Register Name $FE04 Interrupt Status Register 1 (INT1) $FE05 Interrupt Status Register 2 (INT2) $FE06 Interrupt Status Register 3 (INT3) Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Bit 7 0 R 0 IF14 R 0 0 R 0 6 5 IF5 IF4 R R 0 0 0 0 R R 0 0 0 0 R R 0 0 = Unimplemented 4 IF3 R 0 0 R 0 0 R 0 3 0 R 0 0 R 0 0 R 0 R 2 IF1 R 0 0 R 0 0 R 0 = Reserved 1 0 R 0 0 R 0 0 R 0 Bit 0 0 R 0 0 R 0 IF15 R 0 Figure 5-2. SIM I/O Register Summary 5.
System Integration Module (SIM) 5.3 Reset and System Initialization The MCU has these reset sources: • Power-on reset module (POR) • External reset pin (RST) • Computer operating properly module (COP) • Low-voltage inhibit module (LVI) • Illegal opcode • Illegal address All of these resets produce the vector $FFFE–$FFFF ($FEFE–$FEFF in Monitor mode) and assert the internal reset signal (IRST).
Reset and System Initialization IRST RST RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES 2OSCOUT IAB VECTOR HIGH Figure 5-5. Internal Reset Timing The COP reset is asynchronous to the bus clock. ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR INTERNAL RESET LVI Figure 5-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 5.3.2.
System Integration Module (SIM) OSC1 PORRST 4096 CYCLES 32 CYCLES 32 CYCLES 2OSCOUT OSCOUT RST $FFFE IAB $FFFF Figure 5-7. POR Recovery 5.3.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the reset status register (RSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module time-out, write any value to location $FFFF.
SIM Counter 5.3.2.5 LVI Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVI trip voltage VTRIP. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RSTB) is held low while the SIM counter counts out 4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
System Integration Module (SIM) Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared).
Exception Control At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 5-9 shows interrupt entry timing. Figure 5-10 shows interrupt recovery timing.
System Integration Module (SIM) CLI LDA #$FF INT1 BACKGROUND ROUTINE PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 5-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry.
Exception Control Table 5-3.
System Integration Module (SIM) IF14 — Interrupt Flags This flag indicates the presence of interrupt requests from the sources shown in Table 5-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0 to 6 — Always read 0 5.5.2.3 Interrupt Status Register 3 Address: $FE06 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 0 IF15 Write: R R R R R R R R 0 0 0 0 0 0 0 0 R = Reserved Reset: Figure 5-14.
Low-Power Modes 5.6 Low-Power Modes Executing the WAIT or STOP instruction puts the MCU in a low-power-consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 5.6.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 5-15 shows the timing for wait mode entry.
System Integration Module (SIM) 32 Cycles IAB IDB 32 Cycles $6E0B $A6 $A6 RSTVCTH RSTVCT L $A6 RST 2OSCOUT Figure 5-17. Wait Recovery from Internal Reset 5.6.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode.
SIM Registers STOP RECOVERY PERIOD 2OSCOUT INT/BREAK IAB STOP + 2 STOP +1 STOP + 2 SP SP – 1 SP – 2 SP – 3 Figure 5-19. Stop Mode Recovery from Interrupt or Break 5.7 SIM Registers The SIM has three memory mapped registers. Table 5-4 shows the mapping of these registers. Table 5-4. SIM Registers Address Register Access Mode $FE00 BSR User $FE01 RSR User $FE03 BFCR User 5.7.
System Integration Module (SIM) 5.7.2 Reset Status Register (RSR) The SRSR register contains flags that show the source of the last reset. The status register will automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the register. All other reset sources set the individual flag bits but do not clear the register. More than one reset source can be flagged at any time depending on the conditions at the time of the internal or external reset.
SIM Registers 5.7.3 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU is in a break state. Address: Read: Write: Reset: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 5-22. Break Flag Control Register (BFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state.
System Integration Module (SIM) MC68HC908JL3E Family Data Sheet, Rev.
Chapter 6 Oscillator (OSC) 6.1 Introduction The oscillator module provides the reference clock for the MCU system and bus. Two types of oscillator modules are available: • MC68HC908JL3E/JK3E/JK1E — built-in oscillator module (X-tal) that requires an external crystal or ceramic-resonator. This option also allows an external clock that can be driven directly into OSC1. • MC68HRC908JL3E/JK3E/JK1E — built-in oscillator module (RC) that requires an external RC connection only. 6.
Oscillator (OSC) From SIM To SIM To SIM 2OSCOUT XTALCLK OSCOUT ÷2 SIMOSCEN MCU OSC1 OSC2 RB RS* *RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data. X1 See Chapter 16 Electrical Specifications for component value requirements. C1 C2 Figure 6-1.
I/O Signals 6.4 I/O Signals The following paragraphs describe the oscillator I/O signals. 6.4.1 Crystal Amplifier Input Pin (OSC1) OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit. 6.4.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK) For the X-tal oscillator device, OSC2 pin is the output of the crystal oscillator inverting amplifier.
Oscillator (OSC) 6.5 Low Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. 6.5.1 Wait Mode The WAIT instruction has no effect on the oscillator logic. OSCOUT and 2OSCOUT continues to drive to the SIM module. 6.5.2 Stop Mode The STOP instruction disables the XTALCLK or the RCCLK output, hence OSCOUT and 2OSCOUT. 6.6 Oscillator During Break Mode The oscillator continues to drive OSCOUT and 2OSCOUT when the device enters the break state.
Chapter 7 Monitor ROM (MON) 7.1 Introduction This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. This mode is also used for programming and erasing of Flash memory in the MCU.
Monitor ROM (MON) RC CIRCUIT RST VDD FOR MC68HRC908JL3E/JK3E/JK1E SW1 MUST BE AT POSITION B 0.1 μF See Figure 16-1. RC vs. Frequency (5V @25°C) for component values vs. frequency. H(R)C908JL3E H(R)C908JK3E H(R)C908JK1E OSC1 VDD OSC2 VDD 0.
Functional Description 7.3.1 Entering Monitor Mode Table 7-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. If IRQ = VTST: – Clock on OSC1 is 4.9125MHz (EXT OSC or XTAL) – PTB3 = low 2. If IRQ = VTST: – Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL) – PTB3 = high 3. If $FFFE & $FFFF is blank (contains $FF): – Clock on OSC1 is 9.
Monitor ROM (MON) Entering monitor mode with VTST on IRQ, the COP is disabled as long as VTST is applied to either the IRQ or the RST. (See Chapter 5 System Integration Module (SIM) for more information on modes of operation.) If entering monitor mode without high voltage on IRQ and reset vector being blank ($FFFE and $FFFF) (Table 7-1 condition set 3, where applied voltage is VDD), then all port B pin requirements and conditions, including the PTB3 frequency divisor selection, are not in effect.
Functional Description Table 7-2 is a summary of the vector differences between user mode and monitor mode. Table 7-2. Monitor Mode Vector Differences Functions Modes COP Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User Enabled $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor Disabled(1) $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD 1.
Monitor ROM (MON) 7.3.3 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 7-3 and Figure 7-4.) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 STOP BIT BIT 7 NEXT START BIT Figure 7-3. Monitor Data Format $A5 START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BREAK START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 NEXT START BIT STOP BIT STOP BIT NEXT START BIT Figure 7-4.
Functional Description 7.3.6 Commands The monitor ROM uses the following commands: • READ (read memory) • WRITE (write memory) • IREAD (indexed read) • IWRITE (indexed write) • READSP (read stack pointer) • RUN (run user program) Table 7-4. READ (Read Memory) Command Description Read byte from memory Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR.
Monitor ROM (MON) Table 7-6. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Command Sequence SENT TO MONITOR IREAD IREAD DATA DATA RESULT ECHO Table 7-7.
Security Table 7-8. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returned Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence SENT TO MONITOR READSP READSP SP HIGH SP LOW RESULT ECHO Table 7-9. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data Returned None Opcode $28 Command Sequence SENT TO MONITOR RUN RUN ECHO 7.
Monitor ROM (MON) VDD 4096 + 32 OSCXCLK CYCLES RST COMMAND BYTE 8 BYTE 2 BYTE 1 24 BUS CYCLES FROM HOST PTB0 NOTES: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte. 4 1 COMMAND ECHO 2 BREAK 1 BYTE 8 ECHO 1 BYTE 2 ECHO FROM MCU 4 BYTE 1 ECHO 1 Figure 7-7.
Chapter 8 Timer Interface Module (TIM) 8.1 Introduction This section describes the timer interface module (TIM2, Version B). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 8-1 is a block diagram of the TIM. 8.
Timer Interface Module (TIM) 8.4 Functional Description Figure 8-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence.
Functional Description Addr.
Timer Interface Module (TIM) 8.4.1 TIM Counter Prescaler The TIM clock source is one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the TIM clock source. 8.4.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs.
Functional Description control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered output compare operation, do not write new output compare values to the currently active channel registers.
Timer Interface Module (TIM) 8.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 8.4.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods.
Functional Description 8.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3.
Timer Interface Module (TIM) 8.5 Interrupts The following TIM sources can generate interrupt requests: • TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. • TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare occurs on channel x.
I/O Signals 8.8 I/O Signals Port D shares two of its pins with the TIM. The two TIM channel I/O pins are PTD4/TCH0 and PTD5/TCH1. Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTD4/TCH0 can be configured as a buffered output compare or buffered PWM pin. 8.
Timer Interface Module (TIM) TSTOP — TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. When the TSTOP bit is set and the timer is configured for input capture operation, input captures are inhibited until the TSTOP bit is cleared.
I/O Registers 8.9.2 TIM Counter Registers (TCNTH:TCNTL) The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
Timer Interface Module (TIM) 8.9.
I/O Registers MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM channel 0 status and control register. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit.
Timer Interface Module (TIM) TOVx — Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow. 0 = Channel x pin does not toggle on TIM counter overflow.
I/O Registers 8.9.5 TIM Channel Registers (TCH0H/L:TCH1H/L) These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read.
Timer Interface Module (TIM) MC68HC908JL3E Family Data Sheet, Rev.
Chapter 9 Analog-to-Digital Converter (ADC) 9.1 Introduction This section describes the 12-channel, 8-bit linear successive approximation analog-to-digital converter (ADC). 9.2 Features Features of the ADC module include: • 12 channels with multiplexed input • Linear successive approximation with monotonicity • 8-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock Addr.
Analog-to-Digital Converter (ADC) INTERNAL DATA BUS READ DDRB/DDRD DISABLE WRITE DDRB/DDRD DDRBx/DDRDx RESET WRITE PTB/PTD ADCx PTBx/PTDx READ PTB/PTD DISABLE ADC CHANNEL x ADC DATA REGISTER INTERRUPT LOGIC AIEN CONVERSION COMPLETE ADC CHANNEL SELECT (1 OF 12 CHANNELS) ADCH[4:0] ADC CLOCK COCO BUS CLOCK ADC VOLTAGE IN ADCVIN CLOCK GENERATOR ADIV[2:0] ADICLK Figure 9-2. ADC Block Diagram 9.3.
Interrupts 9.3.2 Voltage Conversion When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF (full scale). If the input voltage equals VSS, the ADC converts it to $00. Input voltages between VDD and VSS are a straight-line linear conversion. All other input voltages will result in $FF if greater than VDD and $00 if less than VSS. NOTE Input voltage should not exceed the analog supply voltages. 9.3.
Analog-to-Digital Converter (ADC) 9.5.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode. 9.6 I/O Signals The ADC module has 12 channels that are shared with I/O port B and port D. 9.6.
I/O Registers ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion ADCH[4:0] — ADC Channel Select Bits ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels. The five channel select bits are detailed in the following table.
Analog-to-Digital Converter (ADC) 9.7.2 ADC Data Register One 8-bit result register is provided. This register is updated each time an ADC conversion completes. Address: Read: $003D Bit 7 6 5 4 3 2 1 Bit 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write: Reset: Indeterminate after reset = Unimplemented Figure 9-4. ADC Data Register (ADR) 9.7.
Chapter 10 Input/Output (I/O) Ports 10.1 Introduction Twenty three (23) bidirectional input-output (I/O) pins form three parallel ports. All I/O pins are programmable as inputs or outputs. NOTE Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. 20-pin devices have non-bonded pins.
Input/Output (I/O) Ports Addr. $000A $000D Register Name Bit 7 6 5 4 Read: 0 0 0 0 Port D Control Register Write: (PDCR) Reset: 0 0 0 PTA6EN PTAPUE6 0 0 Port A Input Pull-up Enable Read: Register Write: (PTAPUE) Reset: 3 2 1 Bit 0 SLOWD7 SLOWD6 PTDPU7 PTDPU6 0 0 0 0 0 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 0 0 0 0 0 0 = Unimplemented Figure 10-1. I/O Port Register Summary Table 10-1.
Port A 10.2 Port A Port A is an 7-bit special function port that shares all seven of its pins with the keyboard interrupt (KBI) module (see Chapter 12 Keyboard Interrupt Module (KBI)). Each port A pin also has software configurable pull-up device if the corresponding port pin is configured as input port. PTA0 to PTA5 has direct LED drive capability. NOTE PTA0–PTA5 pins are available on MC68H(R)C908JL3E only. PTA6 pin is available on MC68HRC908JL3E/JK3E/JK1E only. 10.2.
Input/Output (I/O) Ports 10.2.2 Data Direction Register A (DDRA) Data direction register A determines whether each port A pin is an input or an output. Writing a one to a DDRA bit enables the output buffer for the corresponding port A pin; a zero disables the output buffer. Address: $0004 Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 = Unimplemented Figure 10-3.
Port A 10.2.3 Port A Input Pull-up Enable Register (PTAPUE) The port A input pull-up enable register (PTAPUE) contains a software configurable pull-up device for each of the seven port A pins. Each bit is individually configurable and requires the corresponding data direction register, DDRAx be configured as input. Each pull-up device is automatically and dynamically disabled when its corresponding DDRAx bit is configured as output.
Input/Output (I/O) Ports 10.3 Port B Port B is an 8-bit special function port that shares all eight of its port pins with the analog-to-digital converter (ADC) module, see Chapter 9 Analog-to-Digital Converter (ADC). 10.3.1 Port B Data Register (PTB) The port B data register contains a data latch for each of the eight port B pins.
Port B READ DDRB ($0005) INTERNAL DATA BUS WRITE DDRB ($0005) RESET DDRBx WRITE PTB ($0001) PTBx PTBx READ PTB ($0001) To Analog-To-Digital Converter Figure 10-8. Port B I/O Circuit When DDRBx is a 1, reading address $0001 reads the PTBx data latch. When DDRBx is a 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 10-3 summarizes the operation of the port B pins. Table 10-3.
Input/Output (I/O) Ports 10.4 Port D Port D is an 8-bit special function port that shares two of its pins with timer interface module, (see Chapter 8 Timer Interface Module (TIM)) and shares four of its pins with analog-to-digital converter module (see Chapter 9 Analog-to-Digital Converter (ADC)). PTD6 and PTD7 each has high current drive (25mA sink) and programmable pull-up. PTD2, PTD3, PTD6 and PTD7 each has LED driving (sink) capability. NOTE PTD0–PTD1 are available on MC68H(R)C908JL3E only. 10.4.
Port D 10.4.2 Data Direction Register D (DDRD) Data direction register D determines whether each port D pin is an input or an output. Writing a one to a DDRD bit enables the output buffer for the corresponding port D pin; a zero disables the output buffer. Address: Read: Write: Reset: $0007 Bit 7 6 5 4 3 2 1 Bit 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Figure 10-10.
Input/Output (I/O) Ports Table 10-4. Port D Pin Functions DDRD Bit PTD Bit (1) 0 (2) Input, Hi-Z X 1 Accesses to DDRD I/O Pin Mode X Output Accesses to PTD Read/Write Read Write DDRD[7:0] Pin PTD[7:0](3) DDRD[7:0] Pin PTD[7:0] 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input. 10.4.
Chapter 11 External Interrupt (IRQ) 11.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 11.2 Features Features of the IRQ module include the following: • A dedicated external interrupt pin, IRQ • IRQ interrupt control bits • Hysteresis buffer • Programmable edge-only or edge and level interrupt sensitivity • Automatic interrupt acknowledge • Selectable internal pullup resistor 11.
External Interrupt (IRQ) The vector fetch or software clear may occur before or after the interrupt pin returns to one. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear.
IRQ Module During Break Interrupts 11.3.1 IRQ Pin A zero on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set, both of the following actions must occur to clear IRQ: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch.
External Interrupt (IRQ) 11.5 IRQ Status and Control Register (INTSCR) The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module.
Chapter 12 Keyboard Interrupt Module (KBI) 12.1 Introduction The keyboard interrupt module (KBI) provides seven independently maskable external interrupts which are accessible via PTA0–PTA6 pins. 12.
Keyboard Interrupt Module (KBI) 12.4 Functional Description INTERNAL BUS KBI0 ACKK VDD VECTOR FETCH DECODER KEYF RESET . KBIE0 D CLR Q SYNCHRONIZER . CK TO PULLUP ENABLE . KEYBOARD INTERRUPT FF KBI6 KEYBOARD INTERRUPT REQUEST IMASKK MODEK KBIE6 TO PULLUP ENABLE Figure 12-2. Keyboard Interrupt Block Diagram Writing to the KBIE6–KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin.
Keyboard Interrupt Registers The vector fetch or software clear and the return of all enabled keyboard interrupt pins to 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at 0.
Keyboard Interrupt Module (KBI) 12.5.1 Keyboard Status and Control Register • • • • Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity Address: Read: $001A Bit 7 6 5 4 3 0 0 0 0 KEYF Write: Reset: 2 0 ACKK 0 0 0 0 0 0 1 Bit 0 IMASKK MODEK 0 0 = Unimplemented Figure 12-3.
Low-Power Modes 12.5.2 Keyboard Interrupt Enable Register The port-A keyboard interrupt enable register enables or disables each port-A pin to operate as a keyboard interrupt pin. Address: $001B Bit 7 Read: 0 Write: Reset: 6 5 4 3 2 1 Bit 0 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 0 = Unimplemented Figure 12-4.
Keyboard Interrupt Module (KBI) MC68HC908JL3E Family Data Sheet, Rev.
Chapter 13 Computer Operating Properly (COP) 13.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG1 register. 13.2 Functional Description Figure 13-1 shows the structure of the COP module.
Computer Operating Properly (COP) The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 2OSCOUT cycles; depending on the state of the COP rate select bit, COPRS, in configuration register 1. With a 262,128 2OSCOUT cycle overflow option, a 8MHz crystal gives a COP timeout period of 32.766 ms.
COP Control Register 13.3.7 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1. Address: Read: Write: Reset: $001F Bit 7 6 5 4 3 2 1 Bit 0 COPRS R R LVID R SSREC STOP COPD 0 0 0 0 0 0 0 0 R = Reserved Figure 13-2. Configuration Register 1 (CONFIG1) COPRS — COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS.
Computer Operating Properly (COP) 13.7.1 Wait Mode The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. 13.7.2 Stop Mode Stop mode turns off the 2OSCOUT input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. 13.
Chapter 14 Low Voltage Inhibit (LVI) 14.1 Introduction This section describes the low-voltage inhibit module (LVI), which monitors the voltage on the VDD pin and generates a reset when the VDD voltage falls to the LVI trip (LVITRIP) voltage. 14.2 Features Features of the LVI module include the following: • Selectable LVI trip voltage • Selectable LVI circuit disable 14.3 Functional Description Figure 14-1 shows the structure of the LVI module. The LVI is enabled after a reset.
Low Voltage Inhibit (LVI) 14.4 LVI Control Register (CONFIG2/CONFIG1) The LVI module is controlled by three bits in the configuration registers, CONFIG1 and CONFIG2. Address: $001E Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 IRQPUD R R LVIT1 LVIT0 R R R Reset: 0 0 0 Not affected Not affected 0 0 0 POR: 0 0 0 0 0 0 0 0 R = Reserved Figure 14-2.
Chapter 15 Break Module (BREAK) 15.1 Introduction This section describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. 15.2 Features Features of the break module include the following: • Accessible I/O registers during the break Interrupt • CPU-generated break interrupts • Software-generated break interrupts • COP disabling during break interrupts 15.
Break Module (BREAK) Addr.
Break Module Registers 15.4 Break Module Registers These registers control and monitor operation of the break module: • Break status and control register (BRKSCR) • Break address register high (BRKH) • Break address register low (BRKL) • Break status register (BSR) • Break flag control register (BFCR) 15.4.1 Break Status and Control Register (BRKSCR) The break status and control register contains break module enable and status bits.
Break Module (BREAK) 15.4.2 Break Address Registers The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Address: Read: Write: Reset: $FE0C Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Figure 15-4. Break Address Register High (BRKH) Address: Read: Write: Reset: $FE0D Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Figure 15-5.
Low-Power Modes 15.4.4 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU is in a break state. Address: Read: Write: Reset: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 15-7. Break Flag Control Register (BFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state.
Break Module (BREAK) MC68HC908JL3E Family Data Sheet, Rev.
Chapter 16 Electrical Specifications 16.1 Introduction This section contains electrical and timing specifications. 16.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 16.5 5V DC Electrical Characteristics and 16.8 3V DC Electrical Characteristics for guaranteed operating conditions. Table 16-1.
Electrical Specifications 16.3 Functional Operating Range Table 16-2. Operating Range Characteristic Symbol Operating temperature range Operating voltage range Value Unit TA – 40 to +125 – 40 to +85 °C VDD 5 ±10% 3 ±10% V 16.4 Thermal Characteristics Table 16-3.
5V DC Electrical Characteristics 16.5 5V DC Electrical Characteristics Table 16-4. DC Electrical Characteristics (5V) Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (ILOAD = –2.0mA) PTA0–PTA6, PTB0–PTB7, PTD0–PTD7 VOH VDD –0.8 — — V Output low voltage (ILOAD = 1.6mA) PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5 VOL — — 0.4 V Output low voltage (ILOAD = 25mA) PTD6, PTD7 VOL — — 0.
Electrical Specifications Table 16-4. DC Electrical Characteristics (5V) (Continued) Characteristic(1) LVI reset voltage Symbol Min Typ(2) Max Unit VLVR5 3.6 4.0 4.4 V 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only. 3. Run (operating) IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs.
5V Oscillator Characteristics 16.7 5V Oscillator Characteristics Table 16-6.
Electrical Specifications 16.8 3V DC Electrical Characteristics Table 16-7. DC Electrical Characteristics (3V) Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (ILOAD = –1.0mA) PTA0–PTA6, PTB0–PTB7, PTD0–PTD7 VOH VDD – 0.4 — — V Output low voltage (ILOAD = 0.8mA) PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5 VOL — — 0.4 V Output low voltage (ILOAD = 20mA) PTD6, PTD7 VOL — — 0.5 V LED drives (VOL = 1.
3V Control Timing Table 16-7. DC Electrical Characteristics (3V) (Continued) Characteristic(1) LVI reset voltage Symbol Min Typ(2) Max Unit VLVR3 2.0 2.4 2.69 V 1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only. 3. Run (operating) IDD measured using external square wave clock source (fOP = 2MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs.
Electrical Specifications 16.10 3V Oscillator Characteristics Table 16-9.
Typical Supply Currents 16.11 Typical Supply Currents 14 12 IDD (mA) 10 8 6 4 MC68HC908JL3E/JK3E/JK1E 2 5.5 V 3.3 V 0 0 1 2 3 4 5 fOP or fBUS (MHz) 6 7 8 9 Figure 16-3. Typical Operating IDD (MC68HC908JL3E/JK3E/JK1E), with All Modules Turned On (25°C) 10 MC68HRC908JL3E/JK3E/JK1E IDD (mA) 8 5.5 V 3.3 V 6 4 2 0 0 1 2 3 4 5 fOP or fBUS (MHz) 6 7 8 9 Figure 16-4.
Electrical Specifications 2 1.75 MC68HRC908JL3E/JK3E/JK1E 1.50 5.5 V 3.3 V IDD (mA) 1.25 1 0.75 0.5 0.25 0 0 1 2 3 4 fOP or fBUS (MHz) 5 6 7 8 Figure 16-6. Typical Wait Mode IDD (MC68HRC908JL3E/JK3E/JK1E), with All Modules Turned Off (25 °C) 16.12 ADC Characteristics Table 16-10. ADC Characteristics Characteristic Symbol Min Max Unit Supply voltage VDDAD 2.7 (VDD min) 5.5 (VDD max) V Input voltages VADIN VSS VDD V Resolution BAD 8 8 Bits Absolute accuracy AAD ± 0.5 ± 1.
Memory Characteristics 16.13 Memory Characteristics Table 16-11. Memory Characteristics Characteristic Symbol Min Max Unit VRDR 1.
Electrical Specifications MC68HC908JL3E Family Data Sheet, Rev.
Chapter 17 Mechanical Specifications 17.1 Introduction This section gives the dimensions for: • 20-pin plastic dual in-line package (case #738) • 20-pin small outline integrated circuit package (case #751D) • 28-pin plastic dual in-line package (case #710) • 28-pin small outline integrated circuit package (case #751F) • 48-pin low-profile quad flat pack (case #932) The following figures show the latest package drawings at the time of this publication.
Mechanical Specifications MC68HC908JL3E Family Data Sheet, Rev.
Chapter 18 Ordering Information 18.1 Introduction This section contains ordering numbers for the MC68H(R)C908JL3E, MC68H(R)C908JK3E, and MC68H(R)C908JK1E. 18.2 MC Order Numbers Table 18-1.
Ordering Information MC68HC908JL3E Family Data Sheet, Rev.
Appendix A MC68HLC908JL3E/JK3E/JK1E A.1 Introduction This appendix introduces three devices, that are low-voltage versions of MC68HC908JL3E/JK3E/JK1E: • MC68HLC908JL3E • MC68HLC908JK3E • MC68HLC908JK1E The entire data book apply to these low-voltage devices, with exceptions outlined in this appendix. A.2 Flash Memory The Flash memory can be read at minimum VDD of 2.2V. Program or erase operations require a minimum VDD of 2.7V. A.3 Low-Voltage Inhibit There is no low-voltage inhibit circuit.
A.5.2 DC Electrical Characteristics Table A-2. DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (ILOAD = –1.0mA) PTA0–PTA6, PTB0–PTB7, PTD0–PTD7 VOH VDD – 0.4 — — V Output low voltage (ILOAD = 0.8mA) PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5 VOL — — 0.4 V Output low voltage (ILOAD = 15mA) PTD6, PTD7 VOL — — 0.5 V Input high voltage PTA0–PTA6, PTB0–PTB7, PTD0–PTD7, RST, IRQ, OSC1 VIH 0.
A.5.3 Control Timing Table A-3. Control Timing Characteristic(1) Symbol Min Max Unit Internal operating frequency(2) fOP — 2 MHz RST input pulse width low(3) tIRL 1.5 — μs 1. VDD = 2.2 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized.
A.5.5 ADC Characteristics Table A-5. ADC Characteristics Characteristic Symbol Min Max Unit Supply voltage VDDAD 2.2 (VDD min) 5.5 (VDD max) V Input voltages VADIN VSS VDD V Resolution BAD 8 8 Bits Absolute accuracy AAD ± 0.5 ±2 LSB Includes quantization ADC internal clock fADIC 0.5 1.
A.5.6 Memory Characteristics The Flash memory can only be read at an operating voltage of 2.2 to 5.5V. Program and erase are achieved at an operating voltage of 2.7 to 5.5V. The program and erase parameters in Table A-6 are for VDD = 2.7 to 5.5V only. Table A-6. Memory Characteristics Characteristic RAM data retention voltage Flash program bus clock frequency Symbol Min Max Unit VRDR 1.
A.6 MC Order Numbers Table A-7 shows the ordering numbers for the low-voltage devices. Table A-7.
Appendix B MC68H(R)C08JL3E/JK3E B.1 Introduction This appendix introduces four devices, that are ROM versions of MC68H(R)C908JL3E/JK3E: • MC68HC08JL3E • MC68HC08JK3E • MC68HRC08JL3E • MC68HRC08JK3E The entire data book apply to these ROM devices, with exceptions outlined in this appendix. Table B-1.
INTERNAL BUS M68HC08 CPU KEYBOARD INTERRUPT MODULE CONTROL AND STATUS REGISTERS — 64 BYTES 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE USER ROM: PORTA ARITHMETIC/LOGIC UNIT (ALU) DDRA CPU REGISTERS MC68H(R)C08JK3E/JL3E — 4,096 BYTES USER RAM — 128 BYTES PORTB PTB7/ADC7 PTB6/ADC6 PTB5/ADC5 PTB4/ADC4 PTB3/ADC3 PTB2/ADC2 PTB1/ADC1 PTB0/ADC0 PORTD 2-CHANNEL TIMER INTERFACE MODULE PTD7**†‡ PTD6**†‡ PTD5/TCH1 PTD4/TCH0 PTD3/ADC8‡ PTD2/ADC9‡ PTD1/ADC10 PTD0/ADC11 BREAK MODULE OSC1 ¥ OSC2 DDRB MONITO
B.3 Memory Map The MC68H(R)C08JL3E/JK3E has 4,096 bytes of user ROM from $EC00 to $FBFF, and 48 bytes of user ROM vectors from $FFD0 to $FFFF. On the MC68H(R)C908JL3E/JK3E, these memory locations are Flash memory. Figure B-2 shows the memory map of the MC68H(R)C08JL3E/JK3E.
B.4 Reserved Registers The two registers at $FE08 and $FE09 are reserved locations on the MC68H(R)C08JL3E/JK3E. On the MC68H(R)C908JL3E/JK3E, these two locations are the Flash control register and the Flash block protect register respectively. B.5 Mask Option Registers This section describes the mask option registers (MOR1 and MOR2).
SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 × 2OSCOUT cycles instead of a 4096 × 2OSCOUT cycle delay. 1 = Stop mode recovery after 32 × 2OSCOUT cycles 0 = Stop mode recovery after 4096 × 2OSCOUT cycles NOTE Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal, do not set the SSREC bit. STOP — STOP Instruction Enable STOP enables the STOP instruction.
B.7 Electrical Specifications Electrical specifications for the MC68H(R)C908JL3E/JK3E apply to the MC68H(R)C08JL3E/JK3E, except for the parameters indicated below. B.7.1 DC Electrical Characteristics Table B-2.
Table B-3. DC Electrical Characteristics (3V) Characteristic(1) Symbol VDD supply current, fOP = 2MHz Run(3) MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E Wait(4) MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E Stop(5) (–40°C to 85°C) MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E IDD Pullup resistors(6) PTD6, PTD7 RST, IRQ, PTA0–PTA6 RPU1 RPU2 Min Typ(2) Max Unit — — 2.8 1.4 3.5 2 mA mA — — 1.5 0.19 2 0.3 mA mA — — 1.4 1.4 5 5 μA μA 1.8 16 4.3 31 4.8 36 kΩ kΩ 1. VDD = 2.7 to 3.
14 RC FREQUENCY, fRCCLK (MHz) 12 CEXT = 10 pF 10 MCU 5V @ 25°C OSC1 8 6 VDD 4 REXT CEXT 2 0 0 10 20 30 40 50 RESISTOR, REXT (kΩ) Figure B-3. RC vs. Frequency (5V @25°C) 14 RC FREQUENCY, fRCCLK (MHz) 12 CEXT = 10 pF 10 MCU 3V @ 25°C OSC1 8 6 VDD 4 REXT CEXT 2 0 0 10 20 30 40 50 RESISTOR, REXT (kΩ) Figure B-4. RC vs. Frequency (3V @25°C) B.7.3 Memory Characteristics Table B-5. Memory Characteristics Characteristic RAM data retention voltage Symbol Min Max Unit VRDR 1.
B.8 MC Order Numbers These part numbers are generic numbers only. To place an order, ROM code must be submitted to the ROM Processing Center (RPC). Table B-6.
MC68HC908JL3E Family Data Sheet, Rev.
Appendix C MC68HC908KL3E/KK3E C.1 Introduction This appendix introduces two devices, that are ADC-less versions of MC68HC908JL3E/JK3E: • MC68HC908KL3E • MC68HC908KK3E The entire data book applies to these devices, with exceptions outlined in this appendix. Table C-1. Summary of MC68HC908KL3E/KK3E and MC68HC908JL3E Differences MC68HC908KL3E/KK3E MC68HC908JL3E Analog-to-Digital Converter (ADC) — 12-channel, 8-bit. Registers at: $003C, $003E, and $003E Not used; locations are reserved. ADC registers.
INTERNAL BUS M68HC08 CPU ARITHMETIC/LOGIC UNIT (ALU) KEYBOARD INTERRUPT MODULE DDRA CONTROL AND STATUS REGISTERS — 64 BYTES PORTA CPU REGISTERS USER FLASH — 4,096 BYTES USER RAM — 128 BYTES PORTB PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 PORTD 2-CHANNEL TIMER INTERFACE MODULE PTD7**†‡ PTD6**†‡ PTD5/TCH1 PTD4/TCH0 PTD3‡ PTD2‡ PTD1 PTD0 BREAK MODULE DDRB MONITOR ROM — 960 BYTES USER FLASH VECTOR SPACE — 48 BYTES OSC1 X-TAL OSCILLATOR POWER-ON RESET MODULE * RST SYSTEM INTEGRATION MODULE LOW-VOL
1 28 RST PTA0/KBI0 2 27 PTA5/KBI5 VSS 3 26 PTD4/TCH0 OSC1 4 25 PTD5/TCH1 OSC2 5 24 PTD2 PTA1/KBI1 6 23 PTA4 VDD 7 22 PTD3 PTA2/KBI2 8 21 PTB0 PTA3/KBI3 9 20 PTB1 PTB7 10 19 PTD1 PTB6 11 18 PTB2 PTB5 12 17 PTB3 PTD7 13 16 PTD0 PTD6 14 15 PTB4 IRQ MC68HC908KL3E Figure C-2.
C.4 Reserved Registers The following registers are reserved location on the MC68HC908KL3E/KK3E. Addr. Register Name Read: Reserved Write: $003C Bit 7 6 5 4 3 2 1 Bit 0 R R R R R R R R R R R R R R R R R R R R R R R R Reset: Read: Reserved Write: $003D Reset: Read: Reserved Write: $003E Reset: Figure C-4. Reserved Registers C.5 Reserved Vectors The following vectors are reserved interrupt vectors on the MC68HC908KL3E/KK3E. Table C-2.
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