Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908JL3E Family Data Sheet, Rev. 4
102 Freescale Semiconductor
9.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
9.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC
ADIV[2:0] — ADC Clock Prescaler Bits
ADIV[2:0] form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC
clock. Table 9-2 shows the available clock configurations. The ADC clock should be set to
approximately 1MHz.
Address: $003D
Bit 7654321Bit 0
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset: Indeterminate after reset
= Unimplemented
Figure 9-4. ADC Data Register (ADR)
Address: $003E
Bit 7654321Bit 0
Read:
ADIV2 ADIV1 ADIV0
00000
Write:
Reset:00000000
= Unimplemented
Figure 9-5. ADC Input Clock Register (ADICLK)
Table 9-2. ADC Clock Divide Ratio
ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 ADC Input Clock ÷ 1
0 0 1 ADC Input Clock ÷ 2
0 1 0 ADC Input Clock ÷ 4
0 1 1 ADC Input Clock ÷ 8
1 X X ADC Input Clock ÷ 16
X = don’t care