Datasheet

Input/Output (I/O) Ports
MC68HC908JL3E Family Data Sheet, Rev. 4
106 Freescale Semiconductor
10.2.2 Data Direction Register A (DDRA)
Data direction register A determines whether each port A pin is an input or an output. Writing a one to a
DDRA bit enables the output buffer for the corresponding port A pin; a zero disables the output buffer.
DDRA[6:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[6:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 10-4 shows the port A I/O logic.
Figure 10-4. Port A I/O Circuit
When DDRAx is a 1, reading address $0000 reads the PTAx data latch. When DDRAx is a 0, reading
address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the
state of its data direction bit.
Address: $0004
Bit 7654321Bit 0
Read: 0
DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
= Unimplemented
Figure 10-3. Data Direction Register A (DDRA)
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
READ PTA ($0000)
PTAx
DDRAx
PTAx
INTERNAL DATA BUS
30k
PTAPUEx
To Keyboard Interrupt Circuit