Datasheet

External Interrupt (IRQ)
MC68HC908JL3E Family Data Sheet, Rev. 4
116 Freescale Semiconductor
11.5 IRQ Status and Control Register (INTSCR)
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR has the following functions:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks IRQ and interrupt request
• Controls triggering sensitivity of the IRQ
interrupt pin
IRQF — IRQ Flag
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ
interrupt pending
0 = IRQ
interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a one to this write-only bit clears the IRQ latch. ACK always reads as zero. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a one to this read/write bit disables IRQ interrupt requests. Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ
pin. Reset clears MODE.
1 = IRQ
interrupt requests on falling edges and low levels
0 = IRQ
interrupt requests on falling edges only
IRQPUD — IRQ
Pin Pull-up control bit
1 = Internal pull-up is disconnected
0 = Internal pull-up is connected between IRQ
pin and V
DD
Address: $001D
Bit 7654321Bit 0
Read:0000IRQF
IMASK MODE
Write: ACK
Reset:00000000
= Unimplemented
Figure 11-3. IRQ Status and Control Register (INTSCR)
Address: $001E
Bit 7654321Bit 0
Read:
IRQPUDRRLVIT1LVIT0RRR
Write:
Reset:000
Not affected Not affected
000
POR:00000000
R=Reserved
Figure 11-4. Configuration Register 2 (CONFIG2)