Datasheet

Break Module (BREAK)
MC68HC908JL3E Family Data Sheet, Rev. 4
132 Freescale Semiconductor
15.4.2 Break Address Registers
The break address registers contain the high and low bytes of the desired breakpoint address. Reset
clears the break address registers.
15.4.3 Break Status Register
The break status register contains a flag to indicate that a break caused an exit from wait mode.
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
Address: $FE0C
Bit 7654321Bit 0
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Figure 15-4. Break Address Register High (BRKH)
Address: $FE0D
Bit 7654321Bit 0
Read:
Bit 7654321Bit 0
Write:
Reset:00000000
Figure 15-5. Break Address Register Low (BRKL)
Address: $FE00
Bit 7654321Bit 0
Read:
RRRRRR
SBSW
R
Write: Note
(1)
Reset: 0
R = Reserved 1. Writing a zero clears SBSW.
Figure 15-6. Break Status Register (BSR)