Datasheet

MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor 49
Chapter 5
System Integration Module (SIM)
5.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM
is shown in Figure 5-1. Figure 5-2 is a summary of the SIM I/O registers. The SIM is a system state
controller that coordinates CPU and exception timing. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Table 5-1 shows the internal signal names used in this section.
Table 5-1. Signal Name Conventions
Signal Name Description
2OSCOUT Buffered clock from the X-tal oscillator circuit or the RC oscillator circuit.
OSCOUT
The 2OSCOUT frequency divided by two. This signal is again divided by two in the SIM to
generate the internal bus clocks. (Bus clock = 2OSCOUT ÷ 4)
IAB Internal address bus
IDB Internal data bus
PORRST Signal from the power-on reset module to the SIM
IRST Internal reset signal
R/W
Read/write signal