Datasheet

I/O Registers
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor 95
8.9.5 TIM Channel Registers (TCH0H/L:TCH1H/L)
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: $0026 TCH0H
Bit 7654321Bit 0
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset: Indeterminate after reset
Address: $0027 TCH0L
Bit 7654321Bit 0
Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset: Indeterminate after reset
Address: $0029 TCH1H
Bit 7654321Bit 0
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset: Indeterminate after reset
Address: $02A TCH1L
Bit 7654321Bit 0
Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset: Indeterminate after reset
Figure 8-9. TIM Channel Registers (TCH0H/L:TCH1H/L)