MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Data Sheet M68HC08 Microcontrollers MC68HC908KX8 Rev. 2.1 07/2005 freescale.
MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005.
Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date Revision Level Page Number(s) Description Label for pin 9 corrected in Figure 1-1 and Figure 1-2 19, 20 $FF is the erase state of the FLASH, not $00. April, 2001 February, 2002 0.1 1.0 82, 252, 255 First bulleted paragraph under the subsection 15.
List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Chapter 4 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Chapters MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.
Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 3.4 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.2 3.7.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . .
6.3.4 6.3.5 6.4 6.5 6.5.1 6.5.2 6.6 6.7 6.8 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 7.5 7.5.1 7.5.2 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 12.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 12.7.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 12.7.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 12.7.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . .
Chapter 14 Timebase Module (TBM) 14.1 14.2 14.3 14.4 14.5 14.6 14.6.1 14.6.2 14.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . .
Table of Contents 16.2.1.3 TIM1 and TIM2 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.1.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 18 Ordering Information and Mechanical Specifications 18.1 18.2 18.3 18.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Pin Plastic Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Pin Small Outline Package (SOIC) . .
Table of Contents MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.
Chapter 1 General Description 1.1 Introduction The MC68HC908KX8 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCU). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
General Description • • • • • • • • • • • Serial communications interface (SCI) module 5-bit keyboard interrupt (KBI) with wakeup feature 13 general-purpose input/output (I/O) ports: – Five shared with KBI and TIM, with 15-mA source/15-mA sink capabilities and with programmable pullups on general- purpose input ports – Four shared with ADC – Two shared with SCI Low-voltage inhibit (LVI) module with software selectable trip points, 2.6-V or 4.
PTA0/KBD0(2), (3) PTA1/KBD1(2), (3) PTA2/KBD2/TCH0(2), (3) PTA3/KBD3/TCH1(2), (3) PTA4/KBD4(2), (3) POWER-ON RESET MODULE CONTROL AND STATUS REGISTERS — 78 BYTES SECURITY MODULE USER FLASH — 7680 BYTES COMPUTER OPERATING PROPERLY MODULE USER RAM — 192 BYTES PTB ARITHMETIC/LOGIC UNIT DDRB CPU REGISTERS PTB0/AD0 PTB1/AD1 PTB2/AD2 PTB3/AD3 PTB4/RxD PTB5/TxD PTB6/(OSC1)(4) PTB7/(OSC2)/RST(4) PTA M68HC08 CPU LOW-VOLTAGE INHIBIT MODULE MONITOR ROM — 295 BYTES 2-CHANNEL TIMER INTERFACE MODULE USER F
General Description 1.4 Pin Assignments Figure 1-2 shows the pin assignments for MC68HC908KX8. VSS 1 16 VDD PTA1/KBD1 2 15 PTA4/KBD4 PTA0/KBD0 3 14 PTA3/KBD3/TCH1 IRQ1 4 13 PTA2/KBD2/TCH0 PTB0/AD0 5 12 PTB4/RxD PTB1/AD1 6 11 PTB5/TxD PTB2/AD2 7 10 PTB6/(OSC1) PTB3/AD3 8 9 PTB7/(OSC2)/RST Figure 1-2. PDIP and SOIC Pin Assignments 1.4.1 Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply.
Pin Assignments 1.4.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are available through programming options in the configuration register. These pins then become the connections to an external clock source or crystal/ceramic resonator. PTB7 and PTB6 are not available for the crystal/ceramic resonator option and PTB6 is unavailable for the external clock source option. 1.4.3 External Interrupt Pin (IRQ1) IRQ1 is an asynchronous external interrupt pin with an internal pullup resistor.
General Description MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.
Chapter 2 Memory 2.1 Introduction The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: • 7680 bytes of FLASH memory • 192 bytes of random-access memory (RAM) • 36 bytes of user-defined vectors • 295 bytes of monitor read-only memory (ROM) 2.2 I/O Registers Most of the control, status, and data registers are in the zero-page area of $0000–$003F.
Memory $0000 ↓ $003F $0040 ↓ $00FF $0100 ↓ $0FFF $1000 ↓ $13FF I/O REGISTERS (64 BYTES) RAM (192 BYTES) UNIMPLEMENTED (3839 BYTES) FLASH BURN-IN ROM (1024 BYTES) $1400 ↓ $DFFF UNIMPLEMENTED (52,224 BYTES) $E000 ↓ $FDFF USER FLASH MEMORY (7680 BYTES) $FE00 RESERVED $FE01 SIM RESET STATUS REGISTER (SRSR) $FE02 RESERVED $FE03 RESERVED $FE04 INTERRUPT STATUS REGISTER 1 (INT1) $FE05 INTERRUPT STATUS REGISTER 2 (INT2) $FE06 INTERRUPT STATUS REGISTER 3 (INT3) $FE07 RESERVED $FE08 FLASH C
Monitor ROM Addr. $0000 $0001 Register Name Port A Data Register Read: (PTA) Write: See page 106. Reset: Port B Data Register Read: (PTB) Write: See page 108. Reset: $0002 Unimplemented $0003 Unimplemented $0004 Data Direction Register A Read: (DDRA) Write: See page 106. Reset: $0005 $0006 ↓ $000C $000D $000E ↓ $0012 $0013 $0014 $0015 $0016 Data Direction Register B Read: (DDRB) Write: See page 109.
Memory Addr. Bit 7 6 5 4 3 2 1 Bit 0 SCI Status Register 2 Read: (SCS2) Write: See page 132. Reset: 0 0 0 0 0 0 BKF RPF 0 0 0 0 0 0 0 0 SCI Data Register Read: (SCDR) Write: See page 133. Reset: R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 SCI Baud Rate Register Read: (SCBR) Write: See page 133. Reset: 0 0 0 Keyboard Status and Read: Control Register (KBSCR) Write: See page 99.
Monitor ROM Addr. $0022 $0023 $0024 Register Name Timer Counter Register Low Read: (TCNTL) Write: See page 164. Reset: Timer Counter Modulo Read: Register High (TMODH) Write: See page 165. Reset: Timer Counter Modulo Read: Register Low (TMODL) Write: See page 165. Reset: $0025 Timer Channel 0 Status and Read: Control Register (TSC0) Write: See page 165. Reset: $0026 Timer Channel 0 Register Read: High (TCH0H) Write: See page 168.
Memory Addr. $0038 $0039 $003A Register Name ICG Trim Register Read: (ICGTR) Write: See page 89. Reset: ICG Divider Control Read: Register (ICGDVR) Write: See page 89. Reset: ICG DCO Stage Control Read: Register (ICGDSR) Write: See page 89. Reset: $003B $003C $003D $003E $003F $FE00 Reserved Analog-to-Digital Status and Read: Control Register (ADSCR) Write: See page 43. Reset: Analog-to-Digital Data Read: Register (ADR) Write: See page 45.
Monitor ROM Addr. $FE05 $FE06 Register Name Bit 7 6 5 4 3 2 1 Bit 0 Interrupt Status Register 2 Read: (INT2) Write: See page 150. Reset: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 R R R R R R R R 0 0 0 0 0 0 0 0 Interrupt Status Register 3 Read: (INT3) Write: See page 150.
Memory Table 2-1.
Random-Access Memory (RAM) 2.4 Random-Access Memory (RAM) Addresses $0040–$00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE For M6805, M146805 and M68HC05compatibility, the H register is not stacked.
Memory HVEN — High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can be set only if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS — Mass Erase Control Bit Setting this read/write bit configures the 8-Kbyte FLASH array for mass erase operation.
FLASH Mass Erase Operation 2.8 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory to read as a 1: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address(1) within the FLASH memory address range. 4. Wait for a time, tNVS (minimum 10 µs). 5. Set the HVEN bit. 6. Wait for a time, tMErase (minimum 4 ms). 7. Clear the ERASE and MASS bits.
Memory 2.9 FLASH Program/Read Operation Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, and $XXE0. Use this step-by-step procedure to program a row of FLASH memory (Figure 2-4 is a flowchart representation). NOTE Only bytes which are currently $FF may be programmed. 1. Set the PGM bit.
FLASH Program/Read Operation Algorithm for programming a row (32 bytes) of FLASH memory 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 5 6 7 8 WAIT FOR A TIME, tNVS SET HVEN BIT WAIT FOR A TIME, tPGS WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED WAIT FOR A TIME, tPROG COMPLETED PROGRAMMING THIS ROW? YES NO 10 11 CLEAR PGM BIT WAIT FOR A TIME, tNVH Notes: The time between each FLASH address change (
Memory 2.10 FLASH Block Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting a block of memory from unintentional erase or program operations due to system malfunction. This protection is done by using the FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected.
Wait Mode 16-BIT MEMORY ADDRESS START ADDRESS OF FLASH BLOCK PROTECT 1 1 FLBPR VALUE 0 0 0 0 0 0 Figure 2-6. FLASH Block Protect Start Address Table 2-2. Protect Start Address Examples BPR7–BPR0 Start of Address of Protect Range(1) $80 The entire FLASH memory is protected. $81 (1000 0001) $E040 (1110 0000 0100 0000) $82 (1000 0010) $E080 (1110 0000 1000 0000) and so on... $FE (1111 1110) $FF80 (1111 1111 1000 0000) $FF The entire FLASH memory is not protected. 1.
Memory MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.
Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction This section describes the 8-bit analog-to-digital converter (ADC). 3.2 Features Features of the ADC module include: • Four channels with multiplexed input • Linear successive approximation • 8-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock 3.3 Functional Description The ADC provides four pins for sampling external sources at pins PTB3–PTB0.
Freescale Semiconductor SECURITY MODULE USER FLASH — 7680 BYTES COMPUTER OPERATING PROPERLY MODULE LOW-VOLTAGE INHIBIT MODULE MONITOR ROM — 295 BYTES 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 36 BYTES FLASH BURN-IN ROM — 1024 BYTES INTERNAL CLOCK GENERATOR MODULE (SOFTWARE SELECTABLE) KEYBOARD INTERRUPT MODULE ANALOG-TO-DIGITAL CONVERTER MODULE SERIAL COMMUNICATION INTERFACE MODULE SYSTEM INTEGRATION MODULE IRQ MODULE IRQ1(1) VDD VSS PROGRAMMABLE TIME BASE MODULE BREAK MODULE POW
Functional Description INTERNAL DATA BUS READ DDRB WRITE DISABLE DDRBx RESET WRITE PTB PTB PTBx ADC CHANNEL x READ PTB DISABLE READ ADR CONVERSION COMPLETE INTERRUPT LOGIC AIEN ADC DATA REGISTER ADC BUS CLOCK CHANNEL SELECT ADCH[4:0] ADC CLOCK COCO CGMXCLK ADC VOLTAGE IN ADCVIN CLOCK GENERATOR ADIV[2:0] ADICLK Figure 3-2. ADC Block Diagram 3.3.2 Voltage Conversion When the input voltage to the ADC equals VREFH (see 17.
Analog-to-Digital Converter (ADC) Refer to 17.9 Trimmed Accuracy of the Internal Clock Generator. 16 to 17 ADC clock cycles Conversion time = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯ ADC clock frequency Number of bus cycles = conversion time x bus frequency 3.3.4 Continuous Conversion In continuous conversion mode, the ADC data register will be filled with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not.
I/O Signals 3.6 I/O Signals The ADC module has four channels that are shared with port B pins. Refer to 17.9 Trimmed Accuracy of the Internal Clock Generator for voltages referenced here. 3.6.1 ADC Analog Power and ADC Voltage Reference Pins The ADC analog portion uses VDD as its power pin and VSS as its ground pin. Due to pin limitations, the VREFL signal is internally connected to VSS on the MC68HC908KX8. On the MC68HC908KX8, the VREFH signal is internally connected to VDD. 3.6.
Analog-to-Digital Converter (ADC) AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the ADR register is read or the ADSCR register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion.
I/O Registers 3.7.2 ADC Data Register One 8-bit result register is provided. This register is updated each time an ADC conversion completes. Address: $003D Bit 7 6 5 4 3 2 1 Bit 0 Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write: R R R R R R R R Bit 0 Reset: Indeterminate after reset R = Reserved Figure 3-4. ADC Data Register (ADR) 3.7.3 ADC Input Clock Register This register selects the clock frequency for the ADC.
Analog-to-Digital Converter (ADC) The ADC requires a clock rate of approximately 1 MHz for correct operation. If the selected clock source is not fast enough, the ADC will generate incorrect conversions. See 17.9 Trimmed Accuracy of the Internal Clock Generator. fCGMXCLK or bus frequency fADIC = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯ ≅ 1 MHz ADIV[2:0] NOTE During the conversion process, changing the ADC clock will result in an incorrect conversion. MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.
Chapter 4 Configuration Register (CONFIG) 4.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2.
Configuration Register (CONFIG) Address: $001F Bit 7 6 5 4 3 2 1 Bit 0 COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3(1) SSREC STOP COPD Reset: 0 0 0 0 0 0 0 0 Other Resets: 0 0 0 0 U 0 0 0 Read: Write: 1. The LVI5OR3 bit is cleared only by a power-on reset (POR). U = Unaffected Figure 4-2. Configuration Register 1 (CONFIG1) EXTCLKEN — External Clock Enable Bit EXTCLKEN enables an external clock source or crystal/ceramic resonator to be used as a clock input.
Functional Description Clearing the EXTXTALEN bit (default setting) allows the PTB7/(OSC2)/RST pin to function as a general-purpose I/O pin. Refer to Table 4-1 for configuration options for the external source. See Chapter 7 Internal Clock Generator Module (ICG) for a more detailed description of the external clock operation. EXTXTALEN, when set, also configures the clock monitor to expect an external clock source in the valid range of crystals (30 kHz to 100 kHz or 1 MHz to 8 MHz).
Configuration Register (CONFIG) LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. See Chapter 10 Low-Voltage Inhibit (LVI). 1 = LVI module power disabled 0 = LVI module power enabled LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit LVI5OR3 selects the voltage operating mode of the LVI module (see See Chapter 10 Low-Voltage Inhibit (LVI).). The voltage mode selected for the LVI should match the operating VDD.
Chapter 5 Computer Operating Properly Module (COP) 5.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software to recover from a runaway code. Periodically clearing the COP counter will prevent a COP reset from occurring. The COP module can be disabled through the COPD bit in the configuration (CONFIG) register. 5.
Computer Operating Properly Module (COP) 5.3 Functional Description The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 213–24 or 218–24 CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration register. With a 218–24 CGMXCLK cycle overflow option, a 4.9152-MHz CGMXCLK frequency gives a COP timeout period of 53.3 ms.
COP Control Register 5.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 5.4.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See Chapter 4 Configuration Register (CONFIG). 5.4.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register.
Computer Operating Properly Module (COP) 5.8.2 Stop Mode Stop mode holds the 12-bit prescaler counter in reset until after stop mode is exited. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction.
Chapter 6 Central Processor Unit (CPU) 6.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 6.
Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 6-1. CPU Registers 6.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
CPU Registers 6.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
Central Processor Unit (CPU) 6.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 6-6.
Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
Central Processor Unit (CPU) 6.7 Instruction Set Summary Table 6-1 provides a summary of the M68HC08 instruction set.
Instruction Set Summary Effect on CCR V H I N Z C BHS rel Branch if Higher or Same (Same as BCC) BIH rel BIL rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 (A) & (M) BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) Cycles Description Operand Operation Opcode Source Form Address Mode Table
Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Clear Compare A with M Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X D
Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine LDHX #opr LDHX opr Load H:X from M 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT – – – – – – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A ← (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 H:
Central Processor Unit (CPU) V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 6-1.
Opcode Map SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte – – 1 – – – INH 83 9 CCR ← (A) INH 84 2 X ← (A) – – – – – – INH 97 1 A ← (CCR) – – – – – – INH 85 (A) – $00 or (X) – $00 or (M) – $00 DIR INH INH 0 – – – IX1 IX SP1 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH
MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
Chapter 7 Internal Clock Generator Module (ICG) 7.1 Introduction The internal clock generator module (ICG) is used to create a stable clock source for the microcontroller without using any external components. The ICG generates the oscillator output clock (CGMXCLK), which is used by the computer operating properly (COP), low-voltage inhibit (LVI), and other modules. The ICG also generates the clock generator output (CGMOUT), which is fed to the system integration module (SIM) to create the bus clocks.
Internal Clock Generator Module (ICG) CS CGMOUT RESET CGMXCLK CLOCK SELECTION CIRCUIT TBMCLK IOFF EOFF CMON ECGS ICGS CLOCK MONITOR CIRCUIT FICGS DDIV[3:0] INTERNAL CLOCK GENERATOR N[6:0} DSTG[7:0] TRIM[7:0] ICLK IBASE ICGEN SIMOSCEN CLOCK/PIN ENABLE CIRCUIT OSCENINSTOP EXTCLKEN ECGON ICGON ECGEN EXTXTALEN EXTERNAL CLOCK GENERATOR EXTSLOW PTB6 LOGIC INTERNAL TO MCU ECLK PTB7 LOGIC OSC1 PTB6 OSC2 PTB7 EXTERNAL NAME CONFIGURATION (OR MOR) REGISTER BIT NAME REGISTER BIT NAME TOP L
Functional Description 7.3.1 Clock Enable Circuit The clock enable circuit is used to enable the internal clock (ICLK) or external clock (ECLK) and the port logic which is shared with the oscillator pins (OSC1 and OSC2). The clock enable circuit generates an ICG stop (ICGSTOP) signal which stops all clocks (ICLK, ECLK, and the low-frequency base clock, IBASE). ICGSTOP is set and the ICG is disabled in stop mode if the oscillator enable in stop (OSCENINSTOP) bit in the CONFIG (or MOR) register is clear.
Internal Clock Generator Module (ICG) ICGEN VOLTAGE AND CURRENT REFERENCES FICGS ++ DSTG[7:0] DDIV[3:0] DIGITAL LOOP FILTER DIGITALLY CONTROLLED OSCILLATOR ICLK -- TRIM[7:0] FREQUENCY COMPARATOR CLOCK GEN N[6:0] MODULO "N" DIVIDER IBASE NAME CONFIG (OR MOR) REGISTER BIT NAME REGISTER BIT NAME TOP LEVEL SIGNAL NAME MODULE SIGNAL Figure 7-2. Internal Clock Generator Block Diagram 7.3.2.
Functional Description reference with comparators, whose outputs are fed to the digital loop filter. The dependence of these outputs on the capacitor size, current reference, and voltage reference causes up to ±25% error in fNOM. 7.3.2.4 Digital Loop Filter The digital loop filter (DLF) uses the outputs of the frequency comparator to adjust the internal clock (ICLK) clock period. The DLF generates the DCO divider control bits (DDIV[3:0]) and the DCO stage control bits (DSTG[7:0]), which are fed to the DCO.
Internal Clock Generator Module (ICG) ECGEN ECLK INPUT PATH EXTXTALEN AMPLIFIER EXTERNAL CLOCK GENERATOR EXTSLOW INTERNAL TO MCU OSC1 PTB6 OSC2 PTB7 EXTERNAL NAME NAME RB R S* CONFIGURATION (OR MOR) BIT X1 TOP LEVEL SIGNAL NAME REGISTER BIT NAME MODULE SIGNAL C1 *RS can be 0 (shorted) when used with higherfrequency crystals. Refer to manufacturer’s data. C2 These components are required for external crystal use only. Figure 7-3.
Functional Description 7.3.4 Clock Monitor Circuit The ICG contains a clock monitor circuit which, when enabled, will continuously monitor both the external clock (ECLK) and the internal clock (ICLK) to determine if either clock source has been corrupted.
Internal Clock Generator Module (ICG) near 307.2 kHz. For proper operation, EREF must be at least twice as slow as IBASE and IREF must be at least twice as slow as ECLK. To guarantee that IREF is slower than ECLK and EREF is slower than IBASE, one of the signals is divided down. Which signal is divided and by how much is determined by the external slow (EXTSLOW) and external crystal enable (EXTXTALEN) bits in the CONFIG (or MOR) register, according to the rules in Table 7-2.
Functional Description 7.3.4.2 Internal Clock Activity Detector The internal clock activity detector, shown in Figure 7-5, looks for at least one falling edge on the low-frequency base clock (IBASE) every time the external reference (EREF) is low. Since EREF is less than half the frequency of IBASE, this should occur every time. If it does not occur two consecutive times, the internal clock inactivity indicator (IOFF) is set.
Internal Clock Generator Module (ICG) CMON CK IREF EOFF Q 1/4 R R R D D DFFRS CK ECLK DFFRR CK Q S Q EGGS R ESTBCLK ECGEN NAME CONFIGURATION (OR MOR) REGISTER BIT NAME REGISTER BIT NAME TOP LEVEL SIGNAL NAME MODULE SIGNAL Figure 7-6. External Clock Activity Detector 7.3.
Usage Notes 7.3.5.1 Clock Selection Switches The first switch creates the oscillator output clock (CGMXCLK) from either the internal clock (ICLK) or the external clock (ECLK), based on the clock select bit (CS set selects ECLK, clear selects ICLK). When switching the CS bit, both ICLK and ECLK must be on (ICGON and ECGON set). The clock being switched to must also be stable (ICGS or ECGS set). The second switch creates the timebase clock (TBMCLK) from ICLK or ECLK based on the external clock on bit.
Internal Clock Generator Module (ICG) 7.4.1 Switching Clock Sources Switching from one clock source to another requires both clock sources to be enabled and stable. A simple flow requires: 1. Enable desired clock source 2. Wait for it to become stable 3. Switch clocks 4. Disable previous clock source The key point to remember in this flow is that the clock source cannot be switched (CS cannot be written) unless the desired clock is on and stable.
Usage Notes start lda loop ** sta brset cmpa bne ;Clock Monitor Enabling Code Example ;This code turns on both clocks, selects the desired ; one, then turns on the Clock Monitor and Interrupts #$AF ;Mask for CMIE, CMON, ICGON, ICGS, ECGON, ECGS ; If Internal Clock desired, mask is $AF ; If External Clock desired, mask is $BF ; If interrupts not desired mask is $2F int; $3F ext ** ;Other code here, such as writing the COP, since ECGS ; and ICGS may take some time to set. icgcr ;Try to set CMIE.
Internal Clock Generator Module (ICG) 7.4.4 Quantization Error in DCO Output The digitally controlled oscillator (DCO) is comprised of three major sub-blocks: • Binary weighted divider • Variable-delay ring oscillator • Ring oscillator fine-adjust circuit Each of these blocks affects the clock period of the internal clock (ICLK).
Usage Notes 7.4.4.3 Variable-Delay Ring Oscillator The variable-delay ring oscillator’s period is adjustable from 17 to 31 stage delays, in increments of two, based on the upper three DCO stage control bits (DSTG[7:5]). A DSTG[7:5] of %000 corresponds to 17 stage delays; DSTG[7:5] of %111 corresponds to 31 stage delays. Adjusting the DSTG[5] bit has a 6.45% to 11.8% effect on the output frequency. This also corresponds to the size correction made when the frequency error is greater than ±15%.
Internal Clock Generator Module (ICG) period when any of the operating condition changes. This happens whenever the part is reset, the ICG multiply factor (N) is changed, the ICG trim factor (TRIM) is changed, or the internal clock is enabled after inactivity (STOP or disabled operation). The time that the ICLK takes to adjust to the correct period is known as the settling time. Settling time depends primarily on how many corrections it takes to change the clock period, and the period of each correction.
Low-Power Modes period tolerance plus 10%) must be added. This adjustment can be reduced with trimming. Table 7-4 shows some typical values for settling time. Table 7-4. Typical Settling Time Examples τ1 τ2 1/ (6.45 MHz) 1/ (25.8 MHz) 1/ (25.8 MHz) 1/ (6.45 MHz) 1/ (25.8 MHz) 1/ (307.2 kHz) 1/ (307.2 kHz) 1/ (25.8 MHz) τ15 τtot 84 430 µs 1165 µs 21 107 µs 840 µs 1 141 µs 875 µs 84 11.9 ms 12.6 ms N 7.4.
Internal Clock Generator Module (ICG) 7.5.2 Stop Mode The value of the oscillator enable in stop (OSCENINSTOP) bit in the CONFIG (or MOR) register determines the behavior of the ICG in stop mode. If OSCENINSTOP is low, the ICG is disabled in stop and, upon execution of the STOP instruction, all ICG activity will cease and the output clocks (CGMXCLK, CGMOUT, and TBMCLK) will be held low. Power consumption will be minimal. If OSCENINSTOP is high, the ICG is enabled in stop and activity will continue.
I/O Registers 7.6.3 Slow External Clock (EXTSLOW) Slow external clock (EXTSLOW), when set, will decrease the drive strength of the oscillator amplifier, enabling low-frequency crystal operation (30 kHz–100 kHz) if properly enabled with the external clock enable (EXTCLKEN) and external crystal enable (EXTXTALEN) bits. When clear, EXTSLOW enables high-frequency crystal operation (1 MHz to 8 MHz).
Internal Clock Generator Module (ICG) Addr. Register Name Bit 7 ICG DCO Divider Control Read: $0039 Register (ICGDVR) Write: See page 89. Reset: ICG DCO Stage Control Read: Register (ICGDSR) Write: See page 89. Reset: $003A 6 5 4 3 2 1 Bit 0 DDIV3 DDIV2 DDIV1 DDIV0 0 0 0 0 U U U U DSTG7 DSTG6 DSTG5 DSTG4 DSTG3 DSTG2 DSTG1 DSTG0 R R R R R R R R U U U U U U U U R = Reserved = Unimplemented U = Unaffected Figure 7-10.
I/O Registers 7.7.1 ICG Control Register The ICG control register (ICGCR) contains the control and status bits for the internal clock generator, external clock generator, and clock monitor as well as the Clock Select and Interrupt Enable bits. Address: $0036 Bit 7 Read: CMIE Write: Reset: 0 6 5 4 3 (1) CMON CS ICGON 0 0 0 1 CMF 0 = Unimplemented 2 ICGS 0 1 ECGON 0 Bit 0 ECGS 0 1. See CMF bit description for method of clearing Figure 7-11.
Internal Clock Generator Module (ICG) ICGON — Internal Clock Generator On Bit This read/write bit enables the internal clock generator. ICGON can be cleared when the CS bit has been set and the CMON bit has been clear for at least one bus cycle. ICGON is forced set when the CMON bit is set, the CS bit is clear, or during reset.
I/O Registers 7.7.3 ICG Trim Register Address: $0038 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0 0 0 0 0 0 0 0 Reset: 1 = Unimplemented Figure 7-13. ICG Trim Register (ICGTR) TRIM7:TRIM0 — ICG Trim Factor Bits These read/write bits change the size of the internal capacitor used by the internal clock generator.
Internal Clock Generator Module (ICG) DSTG7:DSTG0 — ICG DCO Stage Control Bits These bits indicate the number of stages (above the minimum) in the digitally controlled oscillator. The total number of stages is approximately equal to $1FF, so changing DSTG from $00 to $FF will approximately double the period. Incrementing DSTG will increase the period (decrease the frequency) by 0.202% to 0.368% (decrementing has the opposite effect).
Chapter 8 External Interrupt (IRQ) 8.1 Introduction The external interrupt (IRQ) module provides a maskable interrupt input. 8.2 Features Features of the IRQ module include: • A dedicated external interrupt pin (IRQ1) • IRQ1 interrupt control bits • Internal pullup resistor • Hysteresis buffer • Programmable edge-only or edge- and level-interrupt sensitivity • Automatic interrupt acknowledge 8.
Freescale Semiconductor SECURITY MODULE USER FLASH — 7680 BYTES COMPUTER OPERATING PROPERLY MODULE LOW-VOLTAGE INHIBIT MODULE MONITOR ROM — 295 BYTES 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 36 BYTES FLASH BURN-IN ROM — 1024 BYTES INTERNAL CLOCK GENERATOR MODULE (SOFTWARE SELECTABLE) KEYBOARD INTERRUPT MODULE ANALOG-TO-DIGITAL CONVERTER MODULE SERIAL COMMUNICATION INTERFACE MODULE SYSTEM INTEGRATION MODULE IRQ MODULE IRQ1(1) VDD VSS PROGRAMMABLE TIME BASE MODULE BREAK MODULE POW
IRQ1 Pin INTERNAL ADDRESS BUS ACK1 TO CPU FOR BIL/BIH INSTRUCTIONS VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE VDD IRQF1 D CLR Q SYNCHRONIZER IRQ1 CK IRQ1 INTERRUPT REQUEST IRQ1 LATCH IMASK1 MODE1 HIGH VOLTAGE DETECT TO MODE SELECT LOGIC Figure 8-2. IRQ Block Diagram The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending.
External Interrupt (IRQ) The vector fetch or software clear and the return of the IRQ1 pin to logic 1 can occur in any order. The interrupt request remains pending as long as the IRQ1 pin is at logic 0. A reset will clear the latch and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low. If the MODE1 bit is clear, the IRQ1 pin is falling-edge sensitive only. With MODE1 clear, a vector fetch or software clear immediately clears the IRQ1 latch.
Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides five independently maskable external interrupt pins. 9.
Freescale Semiconductor SECURITY MODULE USER FLASH — 7680 BYTES COMPUTER OPERATING PROPERLY MODULE LOW-VOLTAGE INHIBIT MODULE MONITOR ROM — 295 BYTES 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 36 BYTES FLASH BURN-IN ROM — 1024 BYTES INTERNAL CLOCK GENERATOR MODULE (SOFTWARE SELECTABLE) KEYBOARD INTERRUPT MODULE ANALOG-TO-DIGITAL CONVERTER MODULE SERIAL COMMUNICATION INTERFACE MODULE SYSTEM INTEGRATION MODULE IRQ MODULE IRQ1(1) VDD VSS PROGRAMMABLE TIME BASE MODULE BREAK MODULE POW
Functional Description Addr. $001A $001B Register Name Bit 7 6 5 4 3 2 Keyboard Status and Read: Control Register (KBSCR) Write: See page 99. Reset: 0 0 0 0 KEYF 0 0 0 0 Keyboard Interrupt Enable Read: Register (KBIER) Write: See page 100. Reset: 0 0 0 0 0 ACKK 0 1 Bit 0 IMASKK MODEK 0 0 0 0 0 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 = Unimplemented Figure 9-3. I/O Register Summary 9.
Keyboard Interrupt Module (KBI) The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register.
I/O Registers 9.6 I/O Registers Two registers control and monitor operation of the keyboard module: • Keyboard status and control register, KBSCR • Keyboard interrupt enable register, KBIER 9.6.
Keyboard Interrupt Module (KBI) 9.6.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register (KBIER) enables or disables each port A pin to operate as a keyboard interrupt pin. Address: $001B Read: Bit 7 6 5 0 0 0 0 0 0 Write: Reset: 4 3 2 1 Bit 0 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 = Unimplemented Figure 9-5.
Chapter 10 Low-Voltage Inhibit (LVI) 10.1 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF. 10.2 Features Features of the LVI module include: • Programmable LVI reset • Programmable power consumption • Selectable LVI trip voltage • Programmable stop mode operation 10.3 Functional Description Figure 10-1 shows the structure of the LVI module.
Low-Voltage Inhibit (LVI) Setting the LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage, VTRIPF, to be configured for 5-V operation. Clearing the LVI5OR3 bit enables the trip point voltage, VTRIPF, to be configured for 3-V operation. The actual trip thresholds are specified in 17.5 5.0-Vdc DC Electrical Characteristics and . NOTE After a power-on reset, the LVI’s default mode of operation is 3 volts.
LVI Status Register 10.4 LVI Status Register The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level while LVI resets have been disabled. Address: $FE0C Read: Bit 7 6 5 4 3 2 1 Bit 0 LVIOUT 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 R = Reserved Write: Reset: = Unimplemented Figure 10-2.
Low-Voltage Inhibit (LVI) MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.
Chapter 11 Input/Output (I/O) Ports (PORTS) 11.1 Introduction Thirteen bidirectional input/output (I/O) pins form two parallel ports in the 16-pin plastic dual in-line package (PDIP) and small outline integrated circuit (SOIC) package in the MC68HC908KX8 part. All I/O pins are programmable as inputs or outputs. Port A has software selectable pullup resistors if the port is used as a general-function input port. NOTE Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
Input/Output (I/O) Ports (PORTS) 11.2 Port A Port A is a 5-bit special function port on the MC68HC908KX8 that shares all of its pins with the keyboard interrupt module (KBI) and the 2-channel timer. Port A contains software programmable pullup resistors enabled when a port pin is used as a general-function input. Port A pins are also high-current port pins with 15-mA source/15-mA sink capabilities. 11.2.
Port A DDRA4–DDRA0 — Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA4–DDRA0, configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 11-4 shows the port A I/O logic.
Input/Output (I/O) Ports (PORTS) Address: Read: $000D Bit 7 6 5 0 0 0 0 0 Write: Reset: 0 4 3 2 1 Bit 0 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 0 0 0 0 0 = Unimplemented Figure 11-5. Port A Input Pullup Enable Register (PTAPUE) PTAPUE4–PTAPUE0 — Port A Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit.
Port B TxD — SCI Transmit Data Output Bit The PTB0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTB0/TxD pin is available for general-purpose I/O. See Chapter 12 Serial Communications Interface Module (SCI). AD3–AD0 — Analog-to-Digital Input Bits AD3–AD0 are pins used for the input channels to the analog-to-digital converter (ADC) module.
Input/Output (I/O) Ports (PORTS) When bit DDRBx is a 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 11-2 summarizes the operation of the port B pins. Table 11-2.
Chapter 12 Serial Communications Interface Module (SCI) 12.1 Introduction The serial communications interface (SCI) allows asynchronous communications with peripheral devices and other microcontroller unit (MCU). 12.
Freescale Semiconductor SECURITY MODULE USER FLASH — 7680 BYTES COMPUTER OPERATING PROPERLY MODULE LOW-VOLTAGE INHIBIT MODULE MONITOR ROM — 295 BYTES 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 36 BYTES FLASH BURN-IN ROM — 1024 BYTES INTERNAL CLOCK GENERATOR MODULE (SOFTWARE SELECTABLE) KEYBOARD INTERRUPT MODULE ANALOG-TO-DIGITAL CONVERTER MODULE SERIAL COMMUNICATION INTERFACE MODULE SYSTEM INTEGRATION MODULE IRQ MODULE IRQ1(1) VDD VSS PROGRAMMABLE TIME BASE MODULE BREAK MODULE POW
Pin Name Conventions 12.3 Pin Name Conventions The generic names of the SCI input/output (I/O) pins are: • RxD, receive data • TxD, transmit data SCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an SCI input or output reflects the name of the shared port pin. Table 12-1 shows the full names and the generic names of the SCI I/O pins.The generic pin names appear in the text of this section. Table 12-1.
Serial Communications Interface Module (SCI) INTERNAL BUS ERROR INTERRUPT CONTROL RECEIVE SHIFT REGISTER RxD SCI DATA REGISTER RECEIVER INTERRUPT CONTROL TRANSMITTER INTERRUPT CONTROL SCI DATA REGISTER TRANSMIT SHIFT REGISTER TxD TXINV SCTIE R8 TCIE T8 SCRIE ILIE TE SCTE RE TC RWU SBK SCRF OR ORIE IDLE NF NEIE FE FEIE PE PEIE LOOPS LOOPS WAKEUP CONTROL RECEIVE CONTROL ENSCI ENSCI TRANSMIT CONTROL FLAG CONTROL BKF M RPF WAKE ILTY BAUDCLK ÷4 CGMXCLK A BUSCLK B PRESCALE
Functional Description Addr. Register Name $0013 SCI Control Register 1 (SCC1) See page 125. $0014 SCI Control Register 2 (SCC2) See page 127. $0015 $0016 SCI Control Register 3 (SCC3) See page 129. SCI Status Register 1 (SCS1) See page 130. $0017 SCI Status Register 2 (SCS2) See page 132. $0018 SCI Data Register (SCDR) See page 133. $0019 SCI Baud Rate Register (SCBR) See page 133.
Serial Communications Interface Module (SCI) INTERNAL BUS ÷ 16 SCI DATA REGISTER SCP1 11-BIT TRANSMIT SHIFT REGISTER STOP BAUDCLK BAUD DIVIDER SCP0 SCR1 H SCR2 8 7 6 5 4 3 2 START PRESCALER ÷4 1 0 L TxD MSB SCR0 PARITY GENERATION T8 BREAK ALL 0s PTY PREAMBLE ALL 1s PEN SHIFT ENABLE M LOAD FROM SCDR TRANSMITTER CPU INTERRUPT REQUEST TXINV TRANSMITTER CONTROL LOGIC SCTE SCTE SCTIE TC TCIE SBK LOOPS SCTIE ENSCI TC TE TCIE Figure 12-5.
Functional Description break character and then transmits at least one 1. The automatic 1 at the end of a break character guarantees the recognition of the start bit of the next character. 12.4.2.3 Break Characters The SCI recognizes a break character when a start bit is followed by eight or nine 0 data bits and a 0 where the stop bit should be.
Serial Communications Interface Module (SCI) 12.4.3 Receiver Figure 12-6 shows the structure of the SCI receiver.
Functional Description 12.4.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). 12.4.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the RxD pin.
Serial Communications Interface Module (SCI) To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 12-2 summarizes the results of the start bit verification samples. Table 12-2.
Functional Description To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 12-4 summarizes the results of the stop bit samples. Table 12-4. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 12.4.3.
Serial Communications Interface Module (SCI) With the misaligned character shown in Figure 12-8, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is 154 – 147 -------------------------- × 100 = 4.
Functional Description The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 170 – 176 × 100 = 3.53%. -------------------------170 12.4.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state.
Serial Communications Interface Module (SCI) • • • Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU interrupt requests. Framing error (FE) — The FE bit in SCS1 is set when a 0 occurs where the receiver expects a stop bit.
I/O Registers 12.7 I/O Registers These I/O registers control and monitor SCI operation: • SCI control register 1 (SCC1) • SCI control register 2 (SCC2) • SCI control register 3 (SCC3) • SCI status register 1 (SCS1) • SCI status register 2 (SCS2) • SCI data register (SCDR) • SCI baud rate register (SCBR) 12.7.
Serial Communications Interface Module (SCI) TXINV — Transmit Inversion Bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted NOTE Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits. M — Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 12-5.
I/O Registers Table 12-5. Character Format Selection Control Bits Character Format M PEN–PTY Start Bits Data Bits Parity Stop Bits Character Length 0 0X 1 8 None 1 10 Bits 1 0X 1 9 None 1 11 Bits 0 10 1 7 Even 1 10 Bits 0 11 1 7 Odd 1 10 Bits 1 10 1 8 Even 1 11 Bits 1 11 1 8 Odd 1 11 Bits 12.7.
Serial Communications Interface Module (SCI) SCRIE — SCI Receive Interrupt Enable Bit This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Setting the SCRIE bit in SCC3 enables the SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE bit. 1 = SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt ILIE — Idle Line Interrupt Enable Bit This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests.
I/O Registers 12.7.3 SCI Control Register 3 SCI control register 3 (SCC3): • Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted. • Enables these interrupts: – Receiver overrun interrupts – Noise error interrupts – Framing error interrupts – Parity error interrupts Address: $0015 Bit 7 Read: R8 Write: Reset: U 6 5 4 3 2 1 Bit 0 T8 R R ORIE NEIE FEIE PEIE U 0 0 0 0 0 0 R = Reserved = Unimplemented U = Unaffected Figure 12-12.
Serial Communications Interface Module (SCI) PEIE — Receiver Parity Error Interrupt Enable Bit This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE. Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled NOTE Bits 5 and 4 are reserved for MCUs with a direct-memory access (DMA) module. Because the MC68HC908KX8 does not have a DMA module, these bits should not be set. 12.7.
I/O Registers SCRF — SCI Receiver Full Bit This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is set the SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF.
Serial Communications Interface Module (SCI) BYTE 1 BYTE 2 BYTE 3 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 NORMAL FLAG CLEARING SEQUENCE BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1 READ SCDR BYTE 2 READ SCDR BYTE 3 BYTE 1 BYTE 2 SCRF = 0 OR = 0 SCRF = 1 OR = 1 SCRF = 0 OR = 1 SCRF = 1 SCRF = 1 OR = 1 DELAYED FLAG CLEARING SEQUENCE BYTE 3 BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 1 READ SCDR BY
I/O Registers the SCDR. Once cleared, BKF can become set again only after 1s again appear on the RxD pin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected RPF — Reception-in-Progress Flag Bit This read-only bit is set when the receiver detects a 0 during the RT1 time period of the start bit search. RPF does not generate an interrupt request.
Serial Communications Interface Module (SCI) SCP1 and SCP0 — SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 12-6. Reset clears SCP1 and SCP0. Table 12-6. SCI Baud Rate Prescaling SCP[1:0] Prescaler Divisor (PD) 00 1 01 3 10 4 11 13 SCR2–SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 12-7. Reset clears SCR2–SCR0. Table 12-7.
I/O Registers Table 12-8. SCI Baud Rate Selection Examples SCP[1:0] Prescaler Divisor (PD) SCR[2:1:0] Baud Rate Divisor (BD) Baud Rate (fBAUDCLK = 4.
Serial Communications Interface Module (SCI) MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.
Chapter 13 System Integration Module (SIM) 13.1 Introduction This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. The SIM is a system state controller that coordinates the central processor unit (CPU) and exception timing. Together with the CPU, the SIM controls all microcontroller unit (MCU) activities. Figure 13-1 is a summary of the SIM input/output (I/O) registers. A block diagram of the SIM is shown in Figure 13-2.
System Integration Module (SIM) MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO ICG) SIM COUNTER COP CLOCK CGMXCLK (FROM ICG) CGMOUT (FROM ICG) ÷2 CLOCK CONTROL INTERNAL CLOCKS CLOCK GENERATORS FORCED MON MODE ENTRY (FROM MENRST MODULE) POR CONTROL MASTER RESET CONTROL SIM RESET STATUS REGISTER LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) RESET INTERRUPT CONTROL AND PRIORITY DECODE
SIM Bus Clock Control and Generation 13.2 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 13-3. This clock originates from either an external oscillator or from the internal clock generator.
System Integration Module (SIM) 13.3 Reset and System Initialization The MCU has these internal reset sources: • Power-on reset (POR) module • Computer operating properly (COP) module • Low-voltage inhibit (LVI) module • Illegal opcode • Illegal address • Forced monitor mode entry reset (MENRST) module All of these resets produce the vector $FFFE–$FFFF ($FEFE–$FEFF in monitor mode) and assert the internal reset signal (IRST).
Reset and System Initialization 13.3.1.1 Power-On Reset When power is first applied to the MCU, the power-on reset (POR) module generates a pulse to indicate that power-on has occurred. The MCU is held in reset while the SIM counter counts out 4096 CGMXCLK cycles. Another 64 CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, these events occur: • A POR pulse is generated. • The internal reset signal is asserted.
System Integration Module (SIM) If the stop enable bit, STOP, in the configuration register (CONFIG1) is 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. 13.3.1.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU.
Program Exception Control 13.5 Program Exception Control Normal, sequential program execution can be changed in two ways: 1. Interrupts a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) 2. Reset 13.5.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts.
System Integration Module (SIM) FROM RESET YES BITSET? SET? IIBIT NO IRQ1 INTERRUPT ? NO ICG CLK MON INTERRUPT ? NO OTHER INTERRUPTS ? NO YES YES YES STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION ? YES NO RTI INSTRUCTION ? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 13-9. Interrupt Processing 13.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction.
Low-Power Modes is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the load-accumulator- from-memory (LDA) instruction is executed. The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE To maintain compatibility with the M68HC05, M6805, and M146805 Families the H register is not pushed on the stack during interrupt entry.
System Integration Module (SIM) 13.6.1 Wait Mode In wait mode, the CPU clocks are inactive while one set of peripheral clocks continues to run. Figure 13-11 shows the timing for wait mode entry. IAB WAIT ADDR + 1 WAIT ADDR IDB PREVIOUS DATA SAME SAME NEXT OPCODE SAME SAME R/W Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 13-11.
Low-Power Modes 13.6.2 Stop Mode In stop mode, the SIM counter is held in reset and the CPU and peripheral clocks are held inactive. If the OSCENINSTOP bit in the configuration register is not enabled, the SIM also disables the internal clock generator module outputs (CGMOUT and CGMXCLK). The CPU and peripheral clocks do not become active until after the stop delay timeout. Stop mode is exited via an interrupt request from a module that is still active in stop mode or from a system reset.
System Integration Module (SIM) 13.7 SIM Registers The SIM has four memory mapped registers described here. 1. SIM reset status register (SRSR) 2. Interrupt status register 1 (INT1) 3. Interrupt status register 2 (INT2) 4. Interrupt status register 2 (INT3) 13.7.1 SIM Reset Status Register This register contains five bits that show the source of the last reset. The status register will clear automatically after reading it. A power-on reset sets the POR bit and clears all other bits in the register.
SIM Registers 13.7.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. The interrupt sources and the interrupt status register flags that they set are summarized in Table 13-2. The interrupt status registers can be useful for debugging. Table 13-2.
System Integration Module (SIM) IF6 — Interrupt Flag 6 Since the MC68HC908KX8 parts do not use this interrupt flag, this bit will always read 0. Bit 0 and Bit 1 — Always read 0 13.7.2.2 Interrupt Status Register 2 Address: $FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 13-18.
Chapter 14 Timebase Module (TBM) 14.1 Introduction This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user selectable rates using a counter clocked by either the internal or external clock sources. This TBM version uses 15 divider stages, eight of which are user selectable. 14.
Timebase Module (TBM) TBON 128 ÷2 64 8 ÷2 32 ÷2 16 ÷2 TBMCLK FROM ICG MODULE ÷2 ÷2 TACK ÷2 TBR0 ÷2 TBR1 ÷2 ÷ 32,768 ÷2 ÷ 8192 ÷2 ÷ 2048 ÷2 TBR2 TBMINT TBIF 000 TBIE R 001 010 100 SEL 011 101 110 111 Figure 14-1. Timebase Block Diagram MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.
TBM Interrupt Rate 14.5 TBM Interrupt Rate The interrupt rate is determined by the equation: Divider 1 t TBMRATE = ------------------------ = --------------------f TBMCLK f TBMRATE where: fTBMCLK = Frequency supplied from the internal clock generator (ICG) module Divider = Divider value as determined by TBR2–TBR0 settings. See Table 14-1. As an example, a clock source of 4.9152 MHz and the TBR2–TBR0 set to {011}, the divider tap is 128 and the interrupt rate calculates to 128/4.9152 x 106 = 26 µs.
Timebase Module (TBM) 14.7 Timebase Control Register The timebase has one register, the timebase control register (TBCR), which is used to enable the timebase interrupts and set the rate. Address: $001C Bit 7 Read: TBIF Write: Reset: 0 6 5 4 TBR2 TBR1 TBR0 0 0 0 = Unimplemented 3 2 1 Bit 0 TBIE TBON R 0 0 0 0 R = Reserved 0 TACK Figure 14-2. Timebase Control Register (TBCR) TBIF — Timebase Interrupt Flag This read-only flag bit is set when the timebase counter has rolled over.
Chapter 15 Timer Interface Module (TIM) 15.1 Introduction This section describes the timer interface module (TIM). The TIM is a 2-channel timer that provides a timing reference with input capture, output compare, and pulse-width modulation functions. Figure 15-2 is a block diagram of the TIM. 15.
Freescale Semiconductor SECURITY MODULE USER FLASH — 7680 BYTES COMPUTER OPERATING PROPERLY MODULE LOW-VOLTAGE INHIBIT MODULE MONITOR ROM — 295 BYTES 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 36 BYTES FLASH BURN-IN ROM — 1024 BYTES INTERNAL CLOCK GENERATOR MODULE (SOFTWARE SELECTABLE) KEYBOARD INTERRUPT MODULE ANALOG-TO-DIGITAL CONVERTER MODULE SERIAL COMMUNICATION INTERFACE MODULE SYSTEM INTEGRATION MODULE IRQ MODULE IRQ1(1) VDD VSS PROGRAMMABLE TIME BASE MODULE BREAK MODULE POW
Functional Description PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TMODH:TMODL TOV0 ELS0B CHANNEL 0 ELS0A CH0MAX PORT LOGIC PTA2/KBD2/TCH0 16-BIT COMPARATOR TCH0H:TCH0L CH0F INTERRUPT LOGIC 16-BIT LATCH MS0A CH0IE MS0B INTERNAL BUS TOV1 ELS1B CHANNEL 1 ELS1A CH1MAX PORT LOGIC PTA3/KBD3/TCH1 16-BIT COMPARATOR TCH1H:TCH1L CH1F INTERRUPT LOGIC 16-BIT LATCH MS1A CH1IE Figure 15-2.
Timer Interface Module (TIM) Addr. $0024 $0025 $0026 Register Name Timer Counter Modulo Read: Register Low (TMODL) Write: See page 165. Reset: Timer Channel 0 Status and Read: Control Register (TSC0) Write: See page 165. Reset: Timer Channel 0 Register Read: High (TCH0H) Write: See page 168. Reset: $0027 Timer Channel 0 Register Read: Low (TCH0L) Write: See page 168. Reset: $0028 Timer Channel 1 Status and Read: Control Register (TSC1) Write: See page 165.
Functional Description 15.4.4 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 15.4.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods.
Timer Interface Module (TIM) to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin on overflow if the state of the PWM pulse is logic 0. The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments.
Functional Description in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 15.4.8 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output.
Timer Interface Module (TIM) 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H and TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows.
I/O Registers 15.8 I/O Registers These I/O registers control and monitor operation of the TIM: • TIM status and control register (TSC) • TIM control registers (TCNTH and TCNTL) • TIM counter modulo registers (TMODH and TMODL) • TIM channel status and control registers (TSC0 and TSC1) • TIM channel registers (TCH0H and TCH0L, TCH1H and TCH1L) 15.8.
Timer Interface Module (TIM) TRST — TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000.
I/O Registers 15.8.3 TIM Counter Modulo Registers The read/write TIM modulo registers (TMODH and TMODL) contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Timer Interface Module (TIM) CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x status and control register with CHxF set and then writing a 0 to CHxF.
I/O Registers Table 15-3.
Timer Interface Module (TIM) OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD PTAx/TCH OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE CHxMAX Figure 15-9. CHxMAX Latency 15.8.5 TIM Channel Registers These read/write registers (TCH0H/L and TCH1H/L) contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown.
Chapter 16 Development Support 16.1 Introduction This section describes the break module, the monitor read-only memory (MON), and the monitor mode entry methods. 16.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
Development Support IAB15–IAB8 BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB15–IAB0 CONTROL BREAK 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB7–IAB0 Figure 16-1. Break Module Block Diagram Addr. $FE00 $FE03 Register Name SIM Break Status Register Read: (SBSR) Write: See page 172. Reset: SIM Break Flag Control Read: Register (SBFCR) Write: See page 173. Reset: Break Address Register High Read: $FE09 (BRKH) Write: See page 172.
Break Module (BRK) 16.2.1.3 TIM1 and TIM2 During Break Interrupts A break interrupt stops the timer counters. 16.2.1.4 COP During Break Interrupts The COP is disabled during a break interrupt when BDCOP bit is set in break auxiliary register (BRKAR). 16.2.
Development Support 16.2.2.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Address: Read: Write: Reset: $FE09 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Figure 16-4.
Break Module (BRK) 16.2.2.4 Break Flag Control Register The break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 16-7.
Development Support 16.3 Monitor ROM (MON) The monitor ROM allows complete testing of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing hardware requirements for in-circuit programming.
Monitor ROM (MON) VDD 68HC908KX8 10 kΩ RST (PTB7/OSC2) 0.1 µF VTST 1 kΩ IRQ1 1 10 µF 10 µF MC145407 + 20 + 3 18 4 17 DB-25 2 2 19 5 16 10 µF VDD OSC1 VDD 7 VDD 14 MC74HC125 15 6 VSS 9.8304-MHz CANNED OSCILLATOR 0.1 µF 1 3 VDD 10 µF 0.1 µF + + VDD 2 3 6 5 10 kΩ PTA0 4 PTB1 (PTXMOD1) 7 VDD 10 kΩ PTB0 (PTXMOD0) PTA1 (SERIAL SELECT) Figure 16-9. Normal Monitor Mode Circuit Table 16-1.
Development Support NOTE PTA1 = 0 and PTA0 = 1 allow normal serial communications. PTA1 = 1 allows parallel communications during security code entry. (For parallel communications, configure PTA0 = 0 or PTA0 = 1.) The MCU initially comes out of reset using the external clock for its clock source. This overrides the user mode operation of the oscillator circuits where the part comes up using the internally generated oscillator.
Monitor ROM (MON) 16.3.1.5 Data Format The MCU waits for the host to send eight security bytes (see 16.3.2 Security). After the security bytes, the MCU sends a break signal (10 consecutive 0s) to the host computer, indicating that it is ready to receive a command. Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical.
Development Support 16.3.1.10 Commands The monitor ROM firmware uses these commands: • READ, read memory • WRITE, write memory • IREAD, indexed read • IWRITE, indexed write • READSP, read stack pointer • RUN, run user program The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command.
Monitor ROM (MON) A brief description of each monitor mode command is given in Table 16-4 through Table 16-9. Table 16-4. READ (Read Memory) Command Description Read byte from memory Operand 2-byte address in high-byte:low-byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR READ ADDRESS HIGH READ ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA ECHO RETURN Table 16-5.
Development Support Table 16-7. IWRITE (Indexed Write) Command Description Write to last address accessed + 1 Operand Single data byte Data Returned Opcode None $19 Command Sequence FROM HOST IWRITE IWRITE DATA DATA ECHO A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 16-8.
Monitor ROM (MON) The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6.
Development Support VDD 4096 + 64 CGMXCLK CYCLES IRST 24 CGMXCLK CYCLES PTA1 COMMAND BYTE 8 BYTE 2 BYTE 1 256 CGMXCLK CYCLES (ONE BIT TIME) FROM HOST PTA0 4 1 BREAK 2 COMMAND ECHO 1 BYTE 8 ECHO BYTE 1 ECHO FROM MCU 1 BYTE 2 ECHO 4 1 Notes: 1 = Echo delay (2 bit times) 2 = Data return delay (2 bit times) 4 = Wait 1 bit time before sending next byte. Figure 16-15.
Chapter 17 Electrical Specifications 17.1 Introduction This section contains electrical and timing specifications. 17.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 17.5 5.0-Vdc DC Electrical Characteristics, and for guaranteed operating conditions. Characteristic(1) Symbol Value Unit Supply voltage VDD –0.
Electrical Specifications 17.3 Functional Operating Range Characteristic Symbol Value Unit TA –40 to 125 °C VDD 3.0 ± 10% 5.0 ± 10% V Symbol Value Unit Thermal resistance PDIP (16 pins) SOIC (16 pins) θJA 66 95 °C/W I/O pin power dissipation PI/O User determined W Power dissipation(1) PD PD = (IDD x VDD) + PI/O = K/(TJ + 273°C) W Constant(2) K Average junction temperature Operating temperature range Operating voltage range 17.
5.0-Vdc DC Electrical Characteristics 17.5 5.0-Vdc DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.4 VDD –1.5 VDD –0.8 — — — — — — — — — — — — 0.4 1.5 0.8 Unit Output high voltage ILoad = –2.0 mA, all I/O pins ILoad = –10.0 mA, all I/O pins ILoad = –15.0 mA, PTA0–PTA4 only VOH Output low voltage ILoad = 1.6 mA, all I/O pins ILoad = 10.0 mA, all I/O pins ILoad = 15.0 mA, PTA0–PTA4 only VOL Input high voltage — all ports, IRQ1 VIH 0.7 x VDD — VDD + 0.
Electrical Specifications 17.6 3.0-Vdc DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.3 VDD –1.0 VDD –0.6 — — — — — — — — — — — — 0.3 1.0 0.6 V V V Unit Output high voltage ILoad = –0.6 mA, all I/O pins ILoad = –4.0 mA, all I/O pins ILoad = –10 mA, PTA0–PTA4 only VOH Output low voltage ILoad = 0.5 mA, all I/O pins ILoad = 6.0 mA, all I/O pins ILoad = 10 mA, PTA0–PTA4 only VOL Input high voltage — all ports, IRQ1 VIH 0.7 x VDD — VDD + 0.
Internal Oscillator Characteristics 17.7 Internal Oscillator Characteristics Characteristic(1) Internal oscillator base frequency(2), (3) Internal oscillator tolerance Symbol Min Typ Max Unit fINTOSC 230.4 307.2 384 kHz fOSC_TOL –25 — +25 % N 1 — 127 — Internal oscillator multiplier(4) 1. VDD = 5.5 Vdc to 2.7 Vdc, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted 2. Internal oscillator is selectable through software for a maximum frequency.
Electrical Specifications 17.9 Trimmed Accuracy of the Internal Clock Generator The unadjusted frequency of the low-frequency base clock (IBASE), when the comparators in the frequency comparator indicate zero error, can vary as much as ±25% due to process, temperature, and voltage. The trimming capability exists to compensate for process affects. The remaining variation in frequency is due to temperature, voltage, and change in target frequency (multiply register setting).
Trimmed Accuracy of the Internal Clock Generator Figure 17-1 through Figure 17-4 illustrate typical performance. The formula for this variation of frequency is (measured-nominal)/nominal. Figure 17-1 shows the variation in ICG frequency for a part trimmed at nominal voltage and temperature across VDD and temperature for a 3-V application with multiply register (N) set to 1. Figure 17-2 shows 5 V. 6.00% 4.00% 2.7 2.00% 3 0.00% 3.3 -2.00% -4.00% -6.00% -40 25 85 125 2.7 0.00862069 3 0.
Electrical Specifications Figure 17-3 and Figure 17-4 shows N set to 104, hex 68, which corresponds to an ICG frequency of 31.9 MHz or 7.9 MHz bus. 6.00% 4.00% 2.00% 4.5 0.00% 5 5.5 -2.00% -4.00% -6.00% -40 25 85 125 4.5 0.015021459 0.002145923 -0.025751073 -0.036480687 5 0.015021459 0 -0.021459227 -0.034334764 5.5 0.012875536 0.006437768 -0.019313305 -0.030042918 Figure 17-3. Example of Frequency Variation Across Temperature, Trimmed at Nominal 5 Volts, 25°C, and N = 1 , , 6.
Analog-to-Digital Converter (ADC) Characteristics 17.10 Analog-to-Digital Converter (ADC) Characteristics Characteristic Symbol Min Max Unit Notes Supply voltage VDD 2.7 5.5 V Input voltages VADIN 0 VDD V Resolution BAD 8 8 Bits Absolute accuracy(1), (2) AAD –2.5 +2.5 Counts 8 bits = 256 counts ADC clock rate fADIC 500 k 1.
Electrical Specifications 17.11 Memory Characteristics Characteristic Symbol Min Typ Max Unit VRDR 1.3 — — V — 1 — — MHz fRead(1) 0 — 8M Hz FLASH page erase time <1 K cycles >1 K cycles tErase 0.9 3.6 1 4 1.1 5.
Chapter 18 Ordering Information and Mechanical Specifications 18.1 Introduction This section contains ordering numbers for MC68HC908KX8 and MC68HC908KX2. Refer to Figure 18-1 for an example of the device numbering system. In addition, this section gives the package dimensions for: • 16-pin plastic dual in-line package (case number 648D) • 16-pin small outline package (case number 751G) 18.2 MC Order Numbers Table 18-1.
Ordering Information and Mechanical Specifications 18.3 16-Pin Plastic Dual In-Line Package (PDIP) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.25 (0.010). 6. ROUNDED CORNERS OPTIONAL. -A16 9 -B1 8 F L C S SEATING PLANE -TK H G M J D 16 PL 0.25 (0.
Appendix A MC68HC908KX2 A.1 Introduction This appendix describes the differences between the MC68HC908KX8 and the MC68HC908KX2. A.2 Functional Description The MC68HC908KX2 FLASH memory is an array of 2,048 bytes with an additional 36 bytes of user vectors and one byte used for block protection. See Figure A-1. NOTE An erased bit reads as a 1 and a programmed bit reads as a 0. The program and erase operations are facilitated through control bits in the FLASH control register (FLCR). See 2.
MC68HC908KX2 $0000 ↓ $003F $0040 ↓ $00FF $0100 ↓ $0FFF $1000 ↓ $13FF I/O REGISTERS (64 BYTES) RAM (192 BYTES) UNIMPLEMENTED (3840 BYTES) FLASH BURN-IN ROM (1024 BYTES) $1400 ↓ $F5FF UNIMPLEMENTED (57,856 BYTES) $F600 ↓ $FDFF USER FLASH MEMORY (2048 BYTES) $FE00 RESERVED $FE01 SIM RESET STATUS REGISTER (SRSR) $FE02 RESERVED $FE03 RESERVED $FE04 RESERVED $FE05 RESERVED $FE06 RESERVED $FE07 RESERVED $FE08 FLASH CONTROL REGISTER (FLCR) $FE09 BREAK ADDRESS REGISTER HIGH (BRKH) $FE0A
Appendix B MC68HC08KX8 B.1 Introduction This appendix describes the differences between the read-only memory (ROM) version (MC68HC08KX8) and the FLASH version (MC68HC908KX8) of the microcontroller. Basically, the differences are: • FLASH x ROM module changes – FLASH for ROM substitution – Partial use of FLASH-related module • Configuration register programming • Wider range of operating voltage B.2 FLASH x ROM Module Changes This subsection describes changes between the FLASH and ROM modules. B.2.
Freescale Semiconductor SECURITY MODULE USER ROM — 7680 BYTES COMPUTER OPERATING PROPERLY MODULE LOW-VOLTAGE INHIBIT MODULE MONITOR ROM — 296 BYTES 2-CHANNEL TIMER INTERFACE MODULE USER ROM VECTOR SPACE — 36 BYTES KEYBOARD INTERRUPT MODULE INTERNAL CLOCK GENERATOR MODULE SOFTWARE SELECTABLE SYSTEM INTEGRATION MODULE IRQ MODULE IRQ1 (1) VDD VSS POWER ANALOG-TO-DIGITAL CONVERTER MODULE SERIAL COMMUNICATION INTERFACE MODULE PROGRAMMABLE TIMEBASE MODULE SINGLE BRKPT BREAK MODULE Notes: 1.
Configuration Register Programming B.2.2 Partial Use of FLASH-Related Module 16.3 Monitor ROM (MON) was written having FLASH as user memory and user vector space. MON functions are maintained for the ROM version. MON will allow execution of code in random-access memory (RAM) or ROM and provide ROM memory security(1). The memory programming interface, though, will have no effect in ROM version.
MC68HC08KX8 Address: $001E Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 R LVI2 EXTXTALEN EXTSLOW EXTCLKEN 0 OSCEINSTOP SCIBDSRC Reset: Unaffected by reset R = Reserved Figure B-2. Mask Option Register 2 (MOR2) Address: $001F Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD Unaffected by reset Figure B-3.
Electrical Specifications B.4 Electrical Specifications This subsection contains electrical and timing specifications for the MC68HC08KX8. B.4.1 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to B.4.4 5.0-Vdc DC Electrical Characteristics, and for guaranteed operating conditions.
MC68HC08KX8 B.4.2 Functional Operating Range Characteristic Symbol Value Unit TA –40 to 105 °C VDD 3.0 ± 10% 5.0 ± 10% V Symbol Value Unit Thermal resistance PDIP (16 pins) SOIC (16 pins) θJA 66 95 °C/W I/O pin power dissipation PI/O User determined W Power dissipation(1) PD PD = (IDD x VDD) + PI/O = K/(TJ + 273°C) W Constant(2) K Average junction temperature Operating temperature range Operating voltage range B.4.
Electrical Specifications B.4.4 5.0-Vdc DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.4 VDD –1.5 VDD –0.8 — — — — — — — — — — — — 0.4 1.5 0.8 Unit Output high voltage ILoad = –2.0 mA, all I/O pins ILoad = –10.0 mA, all I/O pins ILoad = –15.0 mA, PTA0–PTA4 only VOH Output low voltage ILoad = 1.6 mA, all I/O pins ILoad = 10.0 mA, all I/O pins ILoad = 15.0 mA, PTA0–PTA4 only VOL Input high voltage — all ports, IRQ1 VIH 0.7 x VDD — VDD + 0.
MC68HC08KX8 B.4.5 3.0-Vdc DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.3 VDD –1.0 VDD –0.6 — — — — — — — — — — — — 0.3 1.0 0.6 V V V Unit Output high voltage ILoad = –0.6 mA, all I/O pins ILoad = –4.0 mA, all I/O pins ILoad = –10 mA, PTA0–PTA4 only VOH Output low voltage ILoad = 0.5 mA, all I/O pins ILoad = 6.0 mA, all I/O pins ILoad = 10 mA, PTA0–PTA4 only VOL Input high voltage — all ports, IRQ1 VIH 0.7 x VDD — VDD + 0.
Electrical Specifications B.4.6 Internal Oscillator Characteristics Characteristic(1) Internal oscillator base frequency(2), (3) Internal oscillator tolerance Internal oscillator multiplier(4) Symbol Min Typ Max Unit fINTOSC 230.4 320 384 kHz fOSC_TOL –25 — +25 % N 1 — 127 — 1. VDD = 5.5 Vdc to 2.7 Vdc, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted 2. Internal oscillator is selectable through software for a maximum frequency.
MC68HC08KX8 B.4.8 Trimmed Accuracy of the Internal Clock Generator The unadjusted frequency of the low-frequency base clock (IBASE), when the comparators in the frequency comparator indicate zero error, can vary as much as ±25% due to process, temperature, and voltage. The trimming capability exists to compensate for process affects. The remaining variation in frequency is due to temperature, voltage, and change in target frequency (multiply register setting).
Electrical Specifications B.4.9 Analog-to-Digital Converter (ADC) Characteristics Characteristic Symbol Min Max Unit Notes Supply voltage VDD 2.7 5.5 V Input voltages VADIN 0 VDD V Resolution BAD 8 8 Bits Absolute accuracy(1), (2) AAD –2.5 +2.5 Counts 8 bits = 256 counts ADC clock rate fADIC 500 k 1.
MC68HC08KX8 MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.
How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp.
