Datasheet

Port A
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 107
DDRA4–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA4–DDRA0, configuring all port
A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 11-4 shows the port A I/O logic.
Figure 11-4. Port A I/O Circuit
When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 11-1 summarizes the operation of the port A pins.
11.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the five port A pins. Each bit is individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically disabled when a port bit’s DDRA is
configured for output mode.
Table 11-1. Port A Pin Functions
PTAPUE
Bit
DDRA
Bit
PTA
Bit
I/O Pin
Mode
Accesses to DDRA Accesses to PTA
Read/Write Read Write
10X
Input, V
DD
(1)
1. I/O pin pulled up to V
DD
by internal pulllup device
DDRA4–DDRA0 Pin
PTA4–PTA0
(2)
2. Writing affects data register, but does not affect input.
0 0 X Input, Hi-Z DDRA4–DDRA0 Pin
PTA4–PTA0
(3)
X 1 X Output DDRA4–DDRA0 PTA4–PTA0 PTA4–PTA0
X = Don’t care
Hi-Z = High impedance
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
READ PTA ($0000)
PTAx
DDRAx
PTAx
INTERNAL DATA BUS
V
DD
PTAPUEx
INTERNAL
PULLUP
DEVICE