Datasheet
Input/Output (I/O) Ports (PORTS)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
108 Freescale Semiconductor
PTAPUE4–PTAPUE0 — Port A Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port A pin configured to have internal pullup
0 = Corresponding port A pin has internal pullup disconnected
11.3 Port B
Port B is an 8-bit special-function port that shares four of its pins with the analog-to-digital converter
module (ADC), two with the serial communication interface module (SCI) and two with an optional
external clock source.
11.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port B pins.
PTB7–PTB0 — Port B Data Bits
These read/write bits are software-programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
OSC2 and OSC1 — OSC2 and OSC1 Bits
Under software control, PTB7 and PTB6 can be configured as external clock inputs and outputs. PTB7
will become an output clock, OSC2, if selected in the configuration registers and enabled in the ICG
registers. PTB6 will become an external input clock source, OSC1, if selected in the configuration
registers and enabled in the ICG registers. See Chapter 7 Internal Clock Generator Module (ICG) and
Chapter 4 Configuration Register (CONFIG).
RxD — SCI Receive Data Input Bit
The PTB1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTB1/RxD pin is available for general-purpose I/O. See
Chapter 12 Serial Communications Interface Module (SCI).
Address: $000D
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0
PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset:0000 0 000
= Unimplemented
Figure 11-5. Port A Input Pullup Enable Register (PTAPUE)
Address: $0001
Bit 7654321Bit 0
Read:
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
Alternate
Function:
OSC2 OSC1 TxD RxD AD3 AD2 AD1 AD0
Figure 11-6. Port B Data Register (PTB)