Datasheet

Serial Communications Interface Module (SCI)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
116 Freescale Semiconductor
Figure 12-5. SCI Transmitter Break Characters
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the
transmit shift register. A logic 1 stop bit goes into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the
transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data
bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a
transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition,
logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and
receiver relinquish control of the port B pins.
Writing a 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A
break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends
on the M bit in SCC1. As long as SBK is at 1, transmitter logic continuously loads break characters into
the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last
PEN
PTY
H876543210L
11-BIT
TRANSMIT
STOP START
T8
SCTE
SCTIE
TCIE
SBK
TC
BAUDCLK
PARITY
GENERATION
MSB
SCI DATA REGISTER
LOAD FROM SCDR SHIFT ENABLE
PREAMBLE
ALL 1s
BREAK
ALL 0s
TRANSMITTER
CONTROL LOGIC
SHIFT REGISTER
TC
SCTIE
TCIE
SCTE
TRANSMITTER CPU INTERRUPT REQUEST
M
ENSCI
LOOPS
TE
TXINV
INTERNAL BUS
÷ 4
PRE-
SCALER
SCP1
SCP0
SCR2
SCR1
SCR0
BAUD
DIVIDER
÷ 16
TxD