Datasheet

Functional Description
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 119
12.4.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2)
is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7).
12.4.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data
register (SCDR) is the read-only buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of the character transfers
to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that
the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the
SCRF bit generates a receiver CPU interrupt request.
12.4.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency
16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at these times
(see Figure 12-7):
• After every start bit
• After the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at
RT8, RT9, and RT10 returns a valid 1 and the majority of the next RT8, RT9, and RT10 samples
returns a valid 0)
To locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s.
When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
Figure 12-7. Receiver Data Sampling
RT CLOCK
RESET
RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT8 RT7 RT6 RT11 RT10 RT9 RT15 RT14 RT13 RT12 RT16 RT1 RT2 RT3 RT4
START BIT
QUALIFICATION
START BIT
VERIFICATION
DATA
SAMPLING
SAMPLES
RT
CLOCK
RT CLOCK
STATE
START BIT
LSB
RxD