Datasheet

Serial Communications Interface Module (SCI)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
132 Freescale Semiconductor
Figure 12-14. Flag Clearing Sequence
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates
a PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
12.7.5 SCI Status Register 2
SCI status register 2 (SCS2) contains flags to signal these conditions:
• Break character detected
• Incoming data
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1,
the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF
does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading
Address: $0017
Bit 7654321Bit 0
Read:000000BKFRPF
Write:
Reset:00000000
= Unimplemented
Figure 12-15. SCI Status Register 2 (SCS2)
BYTE 1
NORMAL FLAG CLEARING SEQUENCE
READ SCS1
SCRF = 1
READ SCDR
BYTE 1
SCRF = 1 SCRF = 1
BYTE 2 BYTE 3 BYTE 4
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 2
SCRF = 0
READ SCS1
SCRF = 1
OR = 0
SCRF = 1 SCRF = 0
READ SCDR
BYTE 3
SCRF = 0
BYTE 1
READ SCS1
SCRF = 1
READ SCDR
BYTE 1
SCRF = 1
SCRF = 1
BYTE 2 BYTE 3 BYTE 4
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 3
DELAYED FLAG CLEARING SEQUENCE
OR = 1
SCRF = 1
OR = 1
SCRF = 0 OR = 1 SCRF = 0 OR = 0