Datasheet

MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 137
Chapter 13
System Integration Module (SIM)
13.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. The SIM is a system state controller that coordinates the central processor unit (CPU)
and exception timing. Together with the CPU, the SIM controls all microcontroller unit (MCU) activities.
Figure 13-1 is a summary of the SIM input/output (I/O) registers. A block diagram of the SIM is shown in
Figure 13-2.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Addr.Register Name Bit 7654321Bit 0
$FE01
SIM Reset Status Register
(SRSR)
See page 148.
Read: POR 0 COP ILOP ILAD MENRST LVI 0
Write:
POR:10000000
$FE04
Interrupt Status Register 1
(INT1)
See page 149.
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
$FE05
Interrupt Status Register 2
(INT2)
See page 150.
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write:RRRRRRRR
Reset:00000000
$FE06
Interrupt Status Register 3
(INT3)
See page 150.
Read: IF22 IF21 IF20 IF19 IF18 IF17 IF16 IF15
Write:RRRRRRRR
Reset:00000000
= Unimplemented R = Reserved
Figure 13-1. SIM I/O Register Summary