Datasheet

System Integration Module (SIM)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
144 Freescale Semiconductor
Figure 13-9. Interrupt Processing
13.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 13-10 demonstrates what happens when two interrupts are pending. If an interrupt
NO
NO
NO
YES
NO
YES
NO
YES
YES
FROM RESET
I BIT SET?
IRQ1
INTERRUPT
ICG CLK MON
INTERRUPT
FETCH NEXT
INSTRUCTION
UNSTACK CPU REGISTERS
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
EXECUTE INSTRUCTION
YES
I BIT SET?
YES
OTHER
INTERRUPTS
NO
SWI
INSTRUCTION
RTI
INSTRUCTION
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?
?
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