Datasheet

System Integration Module (SIM)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
146 Freescale Semiconductor
13.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while one set of peripheral clocks continues to run. Figure 13-11
shows the timing for wait mode entry.
Figure 13-11. Wait Mode Entry Timing
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset. If the COP disable bit, COPD, in the configuration register is a 0,
then the computer operating properly module (COP) is enabled and remains active in wait mode.
Figure 13-12 and Figure 13-13 show the timing for WAIT recovery.
Figure 13-12. Wait Recovery from Interrupt
Figure 13-13. Wait Recovery from Internal Reset
WAIT ADDR + 1 SAME SAMEIAB
IDB
PREVIOUS DATA NEXT OPCODE SAME
WAIT ADDR
SAME
R/W
Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
$DE0C$DE0B $00FF $00FE $00FD $00FC
$A6 $A6 $01 $0B $DE$A6
IAB
IDB
EXITSTOPWAIT
Note: EXITSTOPWAIT = CPU interrupt
IAB
IDB
IRST
$A6 $A6
$DE0B
RST VCT H RST VCT L
$A6
CGMXCLK
64
CYCLES