Datasheet

System Integration Module (SIM)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
148 Freescale Semiconductor
13.7 SIM Registers
The SIM has four memory mapped registers described here.
1. SIM reset status register (SRSR)
2. Interrupt status register 1 (INT1)
3. Interrupt status register 2 (INT2)
4. Interrupt status register 2 (INT3)
13.7.1 SIM Reset Status Register
This register contains five bits that show the source of the last reset. The status register will clear
automatically after reading it. A power-on reset sets the POR bit and clears all other bits in the register.
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MENRST — Forced Monitor Mode Entry Reset Bit
1 = Last reset was caused by the MENRST circuit
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset was caused by the LVI circuit
0 = POR or read of SRSR
Address: $FE01
Bit 7654321Bit 0
Read: POR 0 COP ILOP ILAD MENRST LVI 0
Write:
POR:10000000
= Unimplemented
Figure 13-16. SIM Reset Status Register (SRSR)