Datasheet

SIM Registers
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 149
13.7.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. The interrupt sources and
the interrupt status register flags that they set are summarized in Table 13-2. The interrupt status registers
can be useful for debugging.
13.7.2.1 Interrupt Status Register 1
IF5–IF1 — Interrupt Flags 5, 4, 3, 2, and 1
These flags indicate the presence of interrupt requests from the sources shown in Table 13-2.
1 = Interrupt request present
0 = No interrupt request present
Table 13-2. Interrupt Sources
Source Flag
Mask
(1)
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI
instruction.
INT
Register
Flag
Priority
(2)
2. 0 = highest priority
Vector
Address
SWI instruction — — — 0 $FFFC–$FFFD
IRQ1
pin IRQF1 IMASK1 IF1 1 $FFFA–$FFFB
ICG clock monitor CMF CMIE IF2 2 $FFF8–$FFF9
TIM channel 0 CH0F CH0IE IF3 3 $FFF6–$FFF7
TIM channel 1 CH1F CH1IE IF4 4 $FFF4–$FFF5
TIM overflow TOF TOIE IF5 5 $FFF2–$FFF3
SCI receiver overrun error OR ORIE
IF11 6 $FFE6–$FFE7
SCI receiver noise error NF NEIE
SCI receiver framing error FE FEIE
SCI receiver parity error PE PEIE
SCI receiver full SCRF SCRIE
IF12 7 $FFE4–$FFE5
SCI receiver idle IDLE ILIE
SCI transmitter empty SCTE SCTIE
IF13 8 $FFE2–$FFE3
SCI transmission complete TC TCIE
Keyboard pins KEYF IMASKK IF14 9 $FFE0–$FFE1
ADC conversion complete — AIEN IF15 10 $FFDE–$FFDF
Timebase module TBIE TBF IF16 11 $FFDC–$FFDD
Address: $FE04
Bit 7654321Bit 0
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 13-17. Interrupt Status Register 1 (INT1)