Datasheet
Timer Interface Module (TIM)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
158 Freescale Semiconductor
15.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS2–PS0, in the TIM status and control
register select the TIM clock source.
15.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH and TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
15.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
$0024
Timer Counter Modulo
Register Low (TMODL)
See page 165.
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
$0025
Timer Channel 0 Status and
Control Register (TSC0)
See page 165.
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
$0026
Timer Channel 0 Register
High (TCH0H)
See page 168.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$0027
Timer Channel 0 Register
Low (TCH0L)
See page 168.
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
$0028
Timer Channel 1 Status and
Control Register (TSC1)
See page 165.
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
$0029
Timer Channel 1 Register
High (TCH1H)
See page 168.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$002A
Timer Channel 1 Register
Low (TCH1L)
See page 168.
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
Addr.Register Name Bit 7654321Bit 0
= Unimplemented
Figure 15-3. TIM I/O Register Summary (Continued)