Datasheet

I/O Registers
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 163
15.8 I/O Registers
These I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM control registers (TCNTH and TCNTL)
• TIM counter modulo registers (TMODH and TMODL)
• TIM channel status and control registers (TSC0 and TSC1)
• TIM channel registers (TCH0H and TCH0L, TCH1H and TCH1L)
15.8.1 TIM Status and Control Register
The TIM status and control register (TSC):
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM
counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set
and then writing a 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete,
then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF has no effect.
1 = TIM counter has reached modulo value.
0 = TIM counter has not reached modulo value.
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
Address: $0020
Bit 7654321Bit 0
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
= Unimplemented
Figure 15-5. TIM Status and Control Register (TSC)