Datasheet

Timer Interface Module (TIM)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
164 Freescale Semiconductor
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
PS2–PS0 — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as
Table 15-2 shows. Reset clears the PS2–PS0 bits.
15.8.2 TIM Counter Registers
The two read-only TIM counter registers (TCNTH and TCNTL) contain the high and low bytes of the value
in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a
buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset
clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
Table 15-2. Prescaler Selection
PS2–PS0 TIM Clock Source
000 Internal bus clock ÷1
001 Internal bus clock ÷ 2
010 Internal bus clock ÷ 4
011 Internal bus clock ÷ 8
100 Internal bus clock ÷ 16
101 Internal bus clock ÷ 32
110 Internal bus clock ÷ 64
111 Not available
Register name and address: TCNTH — $0021
Bit 7654321Bit 0
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Register name and address: TCNTL — $0022
Bit 7654321Bit 0
Read:Bit 7654321Bit 0
Write:
Reset:00000000
= Unimplemented
Figure 15-6. TIM Counter Registers (TCNTH and TCNTL)