Datasheet

I/O Registers
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 165
15.8.3 TIM Counter Modulo Registers
The read/write TIM modulo registers (TMODH and TMODL) contain the modulo value for the TIM counter.
When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM
counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits
the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter
modulo registers.
NOTE
Reset the TIM counter before writing to the TIM counter modulo registers.
15.8.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers (TSC0 and TSC1):
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIM overflow
• Selects 0 percent and100 percent PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Register name and address: TMODH — $0023
Bit 7654321Bit 0
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
Register name and address: TMODL — $0024
Bit 7654321Bit 0
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
Figure 15-7. TIM Counter Modulo Registers (TMODH and TMODL)
Register name and address: TSC0 — $0025
Bit 7654321Bit 0
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:0000000 0
Register name and address: TSC1 — $0028
Bit 7654321Bit 0
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:0000000 0
= Unimplemented
Figure 15-8. TIM Channel Status and Control Registers (TSCO and TSC1)