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MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
170 Freescale Semiconductor
Figure 16-1. Break Module Block Diagram
16.2.1.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
Addr.Register Name Bit 7654321Bit 0
$FE00
SIM Break Status Register
(SBSR)
See page 172.
Read:000100BW0
Write:RRRRRRNOTER
Reset:00010000
$FE03
SIM Break Flag Control
Register (SBFCR)
See page 173.
Read:
BCFERRRRRRR
Write:
Reset: 0
$FE09
Break Address Register High
(BRKH)
See page 172.
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
$FE0A
Break Address Register Low
(BRKL)
See page 172.
Read:
Bit 7654321Bit 0
Write:
Reset:00000000
$FE0B
Break Status and Control
Register (BRKSCR)
See page 171.
Read:
BRKE BRKA
000000
Write:
Reset:00000000
$FE02
Break Auxiliary Register
(BRKAR)
See page 173.
Read:0000000
BDCOP
Write:
Reset:00000000
Note: Writing a 0 clears BW.
= Unimplemented R = Reserved
Figure 16-2. I/O Register Summary
IAB15–IAB8
IAB7–IAB0
8-BIT COMPARATOR
8-BIT COMPARATOR
CONTROL
BREAK ADDRESS REGISTER LOW
BREAK ADDRESS REGISTER HIGH
IAB15–IAB0
BREAK