Datasheet

Break Module (BRK)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 173
16.2.2.4 Break Flag Control Register
The break flag control register (SBFCR) contains a bit that enables software to clear status bits while the
MCU is in a break state.
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
16.2.2.5 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the
MCU is in a state of break interrupt with monitor mode.
BDCOP — Break Disable COP Bit
This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt
16.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
16.2.3.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from
the return address on the stack if SBSW is set. Clear the BW bit by writing 0 to it.
16.2.3.2 Stop Mode
A break interrupt causes exit from stop mode and sets the BW bit in the break status register.
Address: $FE03
Bit 7654321Bit 0
Read:
BCFERRRRRRR
Write:
Reset: 0
R= Reserved
Figure 16-7. SIM Break Flag Control Register (SBFCR)
Address: $FE02
Bit 7654321Bit 0
Read:0000000
BDCOP
Write:
Reset:00000000
= Unimplemented
Figure 16-8. Break Auxiliary Register (BRKAR)