Datasheet

Monitor ROM (MON)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 177
16.3.1.5 Data Format
The MCU waits for the host to send eight security bytes (see 16.3.2 Security). After the security bytes, the
MCU sends a break signal (10 consecutive 0s) to the host computer, indicating that it is ready to receive
a command.
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
Figure 16-10. Monitor Data Format
16.3.1.6 Break Signal
A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives
the PTA0 pin high for the duration of two bits and then echoes back the break signal.
Figure 16-11. Break Transaction
16.3.1.7 Baud Rate
The communication baud rate is controlled by the CGMXCLK frequency output of the internal clock
generator module.
16.3.1.8 Force Monitor Mode
In forced monitor mode, the baud rate is fixed at CGMXCLK/1024. A CMGXCLK frequency of 4.9152 MHz
results in a 4800 baud rate. A 9.8304-MHz frequency produces a 9600 baud rate.
16.3.1.9 Normal Monitor Mode
In normal monitor mode, the communication baud rate is controlled by the CGMXCLK frequency output
of the internal clock generator module. Table 16-3 lists CGMXCLK frequencies required to achieve
standard baud rates. Other standard baud rates can be accomplished using other clock frequencies. The
internal clock can be used as the clock source by programming the internal clock generator registers
however, monitor mode will always be entered using the external clock as the clock source.
Table 16-3. Normal Monitor Mode Baud Rate Selection
CGMXCLK Frequency (MHz) Baud Rate
9.8304 9600
BIT 5
START
BIT
BIT 1
NEXT
STOP
BIT
START
BIT
BIT 2 BIT 3 BIT 4 BIT 7BIT 0
BIT 6
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO