Datasheet

Monitor ROM (MON)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 181
The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command
tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can
modify the stacked CPU registers to prepare to run the host program. The READSP command returns
the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at
addresses SP + 5 and SP + 6.
Figure 16-14. Stack Pointer at Monitor Mode Entry
16.3.2 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host
can bypass the security feature at monitor mode entry by sending eight security bytes that match the
bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.
NOTE
Do not leave locations $FFF6–$FFFD blank. For security reasons, program
locations $FFF6–$FFFD even if they are not used for vectors. If FLASH is
erased, the eight security byte values to be sent to the MCU are $FF, the
unprogrammed state of the FLASH.
During monitor mode entry, a reset must be asserted. PTA1 must be held low during the reset and 24
CGMXCLK cycles after the end of the reset. Then the MCU will wait for eight security bytes on PTA0.
Each byte will be echoed back to the host. See Figure 16-15.
If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the security feature and
can read all FLASH locations and execute code from FLASH. Security remains bypassed until a reset
occurs. After any reset, security will be locked. To bypass security again, the host must resend the eight
security bytes on PTA0.
If the received bytes do not match the data at locations $FFF6–$FFFD, the host fails to bypass the
security feature. The MCU remains in monitor mode, but reading FLASH locations returns undefined data,
and trying to execute code from FLASH causes an illegal address reset.
CONDITION CODE REGISTER
ACCUMULATOR
LOW BYTE OF INDEX REGISTER
HIGH BYTE OF PROGRAM COUNTER
LOW BYTE OF PROGRAM COUNTER
SP + 1
SP + 2
SP + 3
SP + 4
SP + 5
SP
SP + 6
HIGH BYTE OF INDEX REGISTER
SP + 7