Datasheet

Functional Description
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 41
Figure 3-2. ADC Block Diagram
3.3.2 Voltage Conversion
When the input voltage to the ADC equals V
REFH
(see 17.9 Trimmed Accuracy of the Internal Clock
Generator), the ADC converts the signal to $FF (full scale). If the input voltage equals V
SS,
the ADC
converts it to $00. Input voltages between V
REFH
and V
SS
are a straight-line linear conversion. All other
input voltages will result in $FF if greater than V
REFH
and $00 if less than V
SS
.
NOTE
Input voltage should not exceed the high-voltage reference, which in turn
should not exceed supply voltages.
3.3.3 Conversion Time
Conversion starts after a write to the ADSCR (ADC status control register, $003C) and requires between
16 and 17 ADC clock cycles to complete. Conversion time in terms of the number of bus cycles is a
function of CGMXCLK frequency, bus frequency, the ADIV prescaler bits, and the ADICLK bit. For
example, with a CGMXCLK frequency of 8 MHz, bus frequency of 2 MHz, and fixed ADC clock frequency
of 1 MHz, one conversion will take between 16 and 17 µs and there will be 32 bus cycles between each
conversion. Sample rate is approximately 60 kHz.
INTERNAL
DATA BUS
RESET
INTERRUPT
LOGIC
CHANNEL
SELECT
ADC
CLOCK
GENERATOR
CONVERSION
COMPLETE
ADC VOLTAGE IN
ADCVIN
ADC CLOCK
CGMXCLK
BUS CLOCK
ADCH[4:0]
ADC DATA REGISTER
ADIV[2:0] ADICLK
AIEN COCO
DISABLE
DISABLE
ADC CHANNEL x
PTB
PTBx
DDRBx
WRITE
READ DDRB
READ PTB
WRITE PTB
READ ADR