Datasheet

I/O Signals
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 43
3.6 I/O Signals
The ADC module has four channels that are shared with port B pins. Refer to 17.9 Trimmed Accuracy of
the Internal Clock Generator for voltages referenced here.
3.6.1 ADC Analog Power and ADC Voltage Reference Pins
The ADC analog portion uses V
DD
as its power pin and V
SS
as its ground pin.
Due to pin limitations, the V
REFL
signal is internally connected to V
SS
on the MC68HC908KX8. On the
MC68HC908KX8, the V
REFH
signal is internally connected to V
DD
.
3.6.2 ADC Voltage In (ADCVIN)
ADCVIN is the input voltage signal from one of the four ADC channels to the ADC module.
3.7 I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register, ADSCR
• ADC data register, ADR
• ADC clock register, ADICLK
3.7.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and control register (ADSCR).
COCO — Conversions Complete Bit
When the AIEN bit is a 0, the COCO is a read-only bit which is set each time a conversion is completed.
This bit is cleared whenever the ADC status and control register is written or whenever the ADC data
register is read.
When the AIEN bit is a 1, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. A CPU interrupt is generated if the COCO bit (ADC status control register, $003C) is at 0.
If the COCO bit is at 1, a DMA interrupt is generated. Reset clears this bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)
or CPU interrupts enabled (AIEN = 1)
NOTE
Because the MC68HC908KX8 does not have a DMA module, the COCO
bit should not be set while interrupts are enabled (AIEN = 1).
Address: $003C
Bit 7654321Bit 0
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write: R
Reset:00011111
R= Reserved
Figure 3-3. ADC Status and Control Register (ADSCR)