Datasheet

I/O Registers
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 45
3.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
3.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock. Table 3-2 shows the available clock configurations. The ADC clock should be
set to approximately 1 MHz.
ADICLK — ADC Input Clock Select Bit
ADICLK selects either bus clock or the oscillator output clock (CGMXCLK) as the input clock source
to generate the internal ADC rate clock. Reset selects CGMXCLK as the ADC clock source.
1 = Internal bus clock
0 = Oscillator output clock (CGMXCLK)
Address: $003D
Bit 7654321Bit 0
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:RRRRRRRR
Reset: Indeterminate after reset
R= Reserved
Figure 3-4. ADC Data Register (ADR)
Address: $003E
Bit 7654321Bit 0
Read:
ADIV2 ADIV1 ADIV0 ADICLK
000
R
Write:
Reset: 0 0000000
= Unimplemented R = Reserved
Figure 3-5. ADC Input Clock Register (ADICLK)
Table 3-2. ADC Clock Divide Ratio
ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 ADC input clock ÷ 1
0 0 1 ADC input clock ÷ 2
0 1 0 ADC input clock ÷ 4
0 1 1 ADC input clock ÷ 8
1 X X ADC input clock ÷ 16
X = don’t care