Datasheet

COP Control Register
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 53
5.4.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
5.4.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See
Chapter 4 Configuration Register (CONFIG).
5.4.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. See
Chapter 4 Configuration Register (CONFIG).
5.5 COP Control Register
The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing
any value to $FFFF clears the COP counter and stages 12–5 of the COP prescaler and starts a new
timeout period. Reading location $FFFF returns the low byte of the reset vector.
5.6 Interrupts
The COP does not generate CPU interrupt requests.
5.7 Monitor Mode
The COP is disabled in monitor mode when V
TST
is present on the IRQ1 pin.
5.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
5.8.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the
COP counter in a CPU interrupt routine.
Address: $FFFF
Bit 7654321Bit 0
Read: Low byte of reset vector
Write: Clear COP counter
Reset: Unaffected by reset
Figure 5-2. COP Control Register (COPCTL)