Datasheet

Internal Clock Generator Module (ICG)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
70 Freescale Semiconductor
Figure 7-2. Internal Clock Generator Block Diagram
7.3.2.1 Digitally Controlled Oscillator
The digitally controlled oscillator (DCO) is an inaccurate oscillator which generates the internal clock
(ICLK). The clock period of ICLK is dependent on the digital loop filter outputs (DSTG[7:0] and DDIV[3:0]).
Because there is only a limited number of bits in DDIV and DSTG, the precision of the output (ICLK) is
restricted to a precision of approximately ±0.202% to ±0.368% when measured over several cycles (of
the desired frequency). Additionally, since the propagation delays of the devices used in the DCO ring
oscillator are a measurable fraction of the bus clock period, reaching the long-term precision may require
alternately running faster and slower than desired, making the worst case cycle-to-cycle frequency
variation ±6.45% to ±11.8% (of the desired frequency). The valid values of DDIV:DSTG range from $000
to $9FF. For more information on the quantization error in the DCO, see 7.4.4 Quantization Error in DCO
Output.
7.3.2.2 Modulo "N" Divider
The modulo "N" divider creates the low frequency base clock (IBASE) by dividing the internal clock (ICLK)
by the ICG multiplier factor (N), contained in the ICG multiplier register (ICGMR). When N is programmed
to a $01 or $00, the divider is disabled and ICLK is passed through to IBASE undivided. When the ICG is
stable, the frequency of IBASE will be equal to the nominal frequency (f
NOM
) of 307.2 kHz ± 25%.
7.3.2.3 Frequency Comparator
The frequency comparator effectively compares the low frequency base clock (IBASE) to a nominal
frequency, f
NOM
. First, the frequency comparator converts IBASE to a voltage by charging a known
capacitor with a current reference for a period dependent on IBASE. This voltage is compared to a voltage
DIGITALLY
CONTROLLED
OSCILLATOR
ICLK
MODULO
"N"
DIVIDER
FREQUENCY
COMPARATOR
CLOCK GEN
TRIM[7:0]
VOLTAGE AND
CURRENT
REFERENCES
++
- -
N[6:0]
DSTG[7:0]
FICGS
ICGEN
IBASE
DDIV[3:0]
NAME
NAME
NAME
NAMECONFIG (OR MOR) REGISTER BIT
TOP LEVEL SIGNAL
REGISTER BIT
MODULE SIGNAL
DIGITAL
LOOP FILTER