Datasheet

Functional Description
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 73
7.3.4 Clock Monitor Circuit
The ICG contains a clock monitor circuit which, when enabled, will continuously monitor both the external
clock (ECLK) and the internal clock (ICLK) to determine if either clock source has been corrupted. The
clock monitor circuit, shown in Figure 7-4, contains these blocks:
• Clock monitor reference generator
• Internal clock activity detector
• External clock activity detector
Figure 7-4. Clock Monitor Block Diagram
7.3.4.1 Clock Monitor Reference Generator
The clock monitor uses a reference based on one clock source to monitor the other clock source. The
clock monitor reference generator generates the external reference clock (EREF) based on the external
clock (ECLK) and the internal reference clock (IREF) based on the internal clock (ICLK). To simplify the
circuit, the low frequency base clock (IBASE) is used in place of ICLK because it always operates at or
EXTXTALEN
EXTSLOW
FICGS
IOFF
CMON
FICGS
IBASE
ICGEN
EREF
IOFF
ICGS
IBASE
EXTXTALEN
EXTSLOW
ECGS
ECLK
ECGEN
ICGON
EREF
ESTBCLK
IREF
ESTBCLK
IREF
ECGEN
ECLK
CMON
ECGS
EOFF
CMON
EOFF
ECGS
ICGS
IBASE
ICGEN
ECLK
ECGEN
ICLK
ACTIVITY
DETECTOR
REFERENCE
GENERATOR
ECLK
ACTIVITY
DETECTOR
NAME
NAME
NAME CONFIGURATION (OR MOR) REGISTER BIT REGISTER BIT
MODULE SIGNAL
NAME TOP LEVEL SIGNAL