Datasheet

Internal Clock Generator Module (ICG)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
74 Freescale Semiconductor
near 307.2 kHz. For proper operation, EREF must be at least twice as slow as IBASE and IREF must be
at least twice as slow as ECLK.
To guarantee that IREF is slower than ECLK and EREF is slower than IBASE, one of the signals is divided
down. Which signal is divided and by how much is determined by the external slow (EXTSLOW) and
external crystal enable (EXTXTALEN) bits in the CONFIG (or MOR) register, according to the rules in
Table 7-2.
NOTE
Each signal (IBASE and ECLK) is always divided by four. A longer divider
is used on either IBASE or ECLK based on the EXTSLOW bit.
To conserve size, the long divider (divide by 4096) is also used as an external crystal stabilization divider.
The divider is reset when the external clock generator is turned off or in STOP (ECGEN is clear). When
the external clock generator is first turned on, the external clock generator stable bit (ECGS) will be clear.
This condition automatically selects ECLK as the input to the long divider. The external stabilization clock
(ESTBCLK) will be ECLK divided by 16 when EXTXTALEN is low or 4096 when EXTXTALEN is high.
This time-out allows the crystal to stabilize. The falling edge of ESTBCLK is used to set ECGS (ECGS will
set after a full 16 or 4096 cycles). When ECGS is set, the divider returns to its normal function. ESTBCLK
may be generated by either IBASE or ECLK, but any clocking will only reinforce the set condition. If ECGS
is cleared because the clock monitor determined that ECLK was inactive, the divider will revert to a
stabilization divider. Since this will change the EREF and IREF divide ratios, it is important to turn the
clock monitor off (CMON = 0) after inactivity is detected to ensure valid recovery.
Table 7-2. Clock Monitor Reference Divider Ratios
ICGON
ECGON
ECGS
EXTSLOW
EXTXTALEN
External
Frequency
EREF
Divider
Ratio
EREF
Frequency
ESTBCLK
Divider
Ratio
ESTBCLK
Frequency
IREF
Divider
Ratio
(1)
1. U = Unaffected; refer to section of table where ICGON or ECGON is set to 1.
IREF
Frequency
0xxxx U U U U U Off 0
x 0 0 x x 0 Off 0 Off 0 U U
110x0
Minimum 60 Hz
Off 0
16
(ECLK)
3.75 Hz
1*4
76.8 kHz
± 25%
Maximum 32 MHz 2.0 MHz
110x1
Minimum 30 kHz
Off 0
4096
(ECLK)
7.324 kHz
1*4
76.8 kHz
± 25%
Maximum 8 MHz 1.953 kHz
11100
Minimum 307.2 kHz
128*4
600 Hz
16
(ECLK)
19.2 kHz
1*4
76.8 kHz
± 25%
Maximum 32 MHz 62.5 kHz 2.0 MHz
11101
Minimum 1 MHz
128*4
1.953 kHz
4096
(ECLK)
244 Hz
1*4
76.8 kHz
± 25%
Maximum 8 MHz 15.63 kHz 1.953 kHz
11110
Minimum 60 Hz
1*4
15 Hz
16
(IBASE)
(2)
2. IBASE is always used as the internal frequency (307.2 kHz).
19.2 kHz
± 25%
4096*4
18.75 Hz
± 125%
Maximum 307.2 kHz 76.8 kHz
11111
Minimum 30 kHz
1*4
7.5 kHz
4096
(IBASE)
(2)
75 Hz
± 25%
16*4
4.8 kHz
± 25%
Maximum 100 kHz 25.0 kHz