Datasheet

Internal Clock Generator Module (ICG)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
76 Freescale Semiconductor
Figure 7-6. External Clock Activity Detector
7.3.5 Clock Selection Circuit
The clock selection circuit, shown in Figure 7-7, contains two clock switches which generate the oscillator
output clock (CGMXCLK) and the timebase clock (TBMCLK) from either the internal clock (ICLK) or the
external clock (ECLK). The clock selection circuit also contains a divide-by-two circuit which creates the
clock generator output clock (CGMOUT), which generates the bus clocks.
Figure 7-7. Clock Selection Circuit Block Diagram
EGGS
EOFF
ECLK
R
D
Q
CK
DFFRR
R
ESTBCLK
R
D
CK
DFFRS
S
Q
CK Q
1/4
R
ECGEN
IREF
CMON
NAME
NAME
NAME
NAMECONFIGURATION (OR MOR) REGISTER BIT
TOP LEVEL SIGNAL
REGISTER BIT
MODULE SIGNAL
ICLK
ECLK
IOFF
EOFF
FORCE_I
FORCE_E
SELECT
OUTPUT
ICLK
ECLK
IOFF
EOFF
FORCE_I
FORCE_E
SELECT
OUTPUT
RESET
ECLK
EOFF
ECGON
ICLK
IOFF
V
SS
CS
DIV2
NAME
NAME
NAME
NAMECONFIGURATION (OR MOR) REGISTER BIT
TOP LEVEL SIGNAL
REGISTER BIT
MODULE SIGNAL
SYNCHRONIZING
CLOCK
SWITCHER
SYNCHRONIZING
CLOCK
SWITCHER
CGMOUT
CGMXCLK
TBMCLK