Datasheet

Internal Clock Generator Module (ICG)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
86 Freescale Semiconductor
$0039
ICG DCO Divider Control
Register (ICGDVR)
See page 89.
Read:
DDIV3 DDIV2 DDIV1 DDIV0
Write:
Reset:0000UUUU
ICG DCO Stage Control
Register (ICGDSR)
See page 89.
Read: DSTG7 DSTG6 DSTG5 DSTG4 DSTG3 DSTG2 DSTG1 DSTG0
Write:RRRRRRRR
$003A Reset: U U U U U U U U
Table 7-5. ICG Module Register Bit Interaction Summary
Condition
Register Bit Results for Given Condition
CMIE CMF CMON CS ICGON ICGS ECGON ECGS N[6:0] TRIM[7:0] DDIV[3:0] DSTB[7:0]
Reset 0 0 0 0 1 0 0 0 $15 $80 — —
OSCENINSTOP = 0,
STOP = 1
00 0—— 0 — 0 — — — —
EXTCLKEN = 0 0 0 0 0 1 — 0 0 — — uw uw
CMF = 1 — (1) 1 — 1 — 1 — uw uw uw uw
CMON = 0 0 0 (0) — — — — — — — — —
CMON = 1 — — (1) — 1 — 1 — uw uw uw uw
CS = 0 — — — (0) 1 — — — — — uw uw
CS = 1 — — — (1) — — 1 — — — — —
ICGON = 0 0 0 0 1 (0) 0 1 — — — — —
ICGON = 1 —— ——(1) — — — — — uw uw
ICGS = 0 us — us uc — (0) — — — — — —
ECGON = 0 0 0 0 0 1 — (0) 0 — — uw uw
ECGS = 0 us — us us — — — (0) — — — —
IOFF = 1 — 1* (1) 1 (1) 0 (1) — uw uw uw uw
EOFF = 1 — 1* (1) 0 (1) — (1) 0 uw uw uw uw
N = written (0) (0) (0) — — 0* — — — — — —
TRIM = written (0) (0) (0) — — 0* — — — — — —
—Register bit is unaffected by the given condition.
0, 1Register bit is forced clear or set (respectively) in the given condition.
0*, 1*Register bit is temporarily forced clear or set (respectively) in the given condition.
(0), (1)Register bit must be clear or set (respectively) for the given condition to occur.
us, uc, uwRegister bit cannot be set, cleared, or written (respectively) in the given condition.
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented R = Reserved U = Unaffected
Figure 7-10. ICG Module I/O Register Summary (Continued)