Datasheet

I/O Registers
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 89
7.7.3 ICG Trim Register
TRIM7:TRIM0 — ICG Trim Factor Bits
These read/write bits change the size of the internal capacitor used by the internal clock generator. By
testing the frequency of the internal clock and incrementing or decrementing this factor accordingly,
the accuracy of the internal clock can be improved to ±2%. Incrementing this register by one decreases
the frequency by 0.195% of the unadjusted value. Decrementing this register by one increases the
frequency by 0.195%. This register cannot be written when the CMON bit is set. Reset sets these bits
to $80, centering the range of possible adjustment.
7.7.4 ICG DCO Divider Register
DDIV3:DDIV0 — ICG DCO Divider Control Bits
These bits indicate the number of divide-by-twos (DDIV) that follow the digitally controlled oscillator.
When ICGON is set, DDIV is controlled by the digital loop filter. The range of valid values for DDIV is
from $0 to $9. Values of $A–$F are interpreted the same as $9. Since the DCO is active during reset,
reset has no effect on DSTG and the value may vary.
7.7.5 ICG DCO Stage Register
Address: $0038
Bit 7654321Bit 0
Read:
TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0
Write:
Reset:10000000
= Unimplemented
Figure 7-13. ICG Trim Register (ICGTR)
Address: $0039
Bit 7654321Bit 0
Read: DDIV3 DDIV2 DDIV1 DDIV0
Write:
Reset:0000UUUU
= Unimplemented U = Undefined
Figure 7-14. ICG DCO Divider Control Register (ICGDVR)
Address: $003A
Bit 7654321Bit 0
Read: DSTG7 DSTG6 DSTG5 DSTG4 DSTG3 DSTG2 DSTG1 DSTG0
Write:RRRRRRRR
Reset:UUUUUUUU
= Unimplemented
R
= Reserved U = Unaffected
Figure 7-15. ICG DCO Stage Control Register (ICGDSR)