Datasheet

IRQ1 Pin
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor 93
Figure 8-2. IRQ Block Diagram
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1 control
bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK1 bit in the ISCR masks all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK1 bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
8.4 IRQ1 Pin
A logic 0 on the IRQ1 pin can latch an interrupt request into the IRQ1 latch. A vector fetch, software clear,
or reset clears the IRQ1 latch.
If the MODE1 bit is set, the IRQ1
pin is both falling-edge sensitive and low-level sensitive. With MODE1
set, both of the following actions must occur to clear the IRQ1 latch:
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a 1 to the ACK1 bit
in the interrupt status and control register (ISCR). The ACK1 bit is useful in applications that poll
the IRQ1
pin and require software to clear the IRQ1 latch. Writing to the ACK1 bit can also prevent
spurious interrupts due to noise. Setting ACK1 does not affect subsequent transitions on the IRQ1
pin. A falling edge on the IRQ1
pin that occurs after writing to the ACK1 bit latches another interrupt
request. If the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program counter with the vector
address at locations $FFFA and $FFFB.
• Return of the IRQ1
pin to logic 1 — As long as the IRQ1 pin is at logic 0, the IRQ1 latch remains
set.
ACK1
IMASK1
DQ
CK
CLR
IRQ1
HIGH
INTERRUPT
TO MODE
SELECT
LOGIC
IRQ1
LATCH
REQUEST
IRQ1
V
DD
MODE1
VOLTAGE
DETECT
IRQF1
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
INTERNAL ADDRESS BUS
V
DD
INTERNAL
PULLUP
DEVICE
SYNCHRONIZER