MC68HC908LJ24 MC68HC908LK24 Data Sheet M68HC08 Microcontrollers Rev. 2.1 MC68HC908LJ24/D August 16, 2005 freescale.
MC68HC908LJ24 MC68HC908LK24 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History Revision History Date Revision Level 8/2003 2 Data Sheet 4 Description First general release. Page Number(s) — MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . . 37 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Section 3. Random-Access Memory (RAM) . . . . . . . . . . 67 Section 4. FLASH Memory (FLASH) . . . . . . . . . . . . . . . . 69 Section 5. Configuration Registers (CONFIG) . . . . . . . . 79 Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 85 Section 7. Oscillator (OSC) . . . . . . . . . . . . . . .
List of Sections Section 20. Keyboard Interrupt Module (KBI). . . . . . . . 407 Section 21. Computer Operating Properly (COP) . . . . 415 Section 22. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . 421 Section 23. Break Module (BRK) . . . . . . . . . . . . . . . . . . 427 Section 24. Electrical Specifications. . . . . . . . . . . . . . . 435 Section 25. Mechanical Specifications . . . . . . . . . . . . . 451 Section 26. Ordering Information . . . . . . . . . . . . . . . . . 457 Appendix A.
Data Sheet — MC68HC908LJ24 Table of Contents Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.5 Pin Assignments . . . . . . . .
Table of Contents Section 2. Memory Map 2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 49 2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents Section 6. Central Processor Unit (CPU) 6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.4.1 Accumulator . . . . . . . . . . . . . . . . . .
Table of Contents 7.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 7.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 7.7 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . 107 Section 8. Clock Generator Module (CGM) 8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 8.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 8.8.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . 134 8.
Table of Contents 9.6.1.3 9.6.1.4 9.6.1.5 9.6.1.6 9.6.2 9.6.3 9.6.4 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . .153 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 153 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . 155 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . 155 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Break Interrupts . . . . . . . . . . . .
Table of Contents Section 11. Timer Interface Module (TIM) 11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.5 Functional Description . . . . . . . . . . . . . .
Table of Contents Section 12. Real Time Clock (RTC) 12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12.4 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 12.5 Functional Description . . . . . . . . . . . .
Table of Contents Section 13. Infrared Serial Communications Interface Module (IRSCI) 13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 13.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.
Table of Contents 13.10.2 PTB1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.11 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 13.11.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 13.11.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 13.11.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 13.11.4 SCI Status Register 1. . . .
Table of Contents 14.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 14.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 308 14.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 14.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . . 309 14.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . . 309 14.13.3 SPSCK (Serial Clock). . .
Table of Contents 16.4 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 16.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 16.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 16.4.5 Result Justification . . . . . . . . .
Table of Contents 17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 17.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 17.7.1 BP0–BP3 (Backplane Drivers) . . . . . . . . . . . . . . . . . . . . . . 359 17.7.
Table of Contents 18.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 18.8.1 Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . . 397 18.8.2 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . 398 18.8.3 Port F LED Control Register (LEDF) . . . . . . . . . . . . . . . . . 399 Section 19. External Interrupt (IRQ) 19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401 19.
Table of Contents Section 21. Computer Operating Properly (COP) 21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415 21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 21.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416 21.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 21.4.1 ICLK . . . . . . . . . . . . . . . . . . . .
Table of Contents 22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 22.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 22.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 Section 23. Break Module (BRK) 23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427 23.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 24.9 3.3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 24.10 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 441 24.11 3.3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 442 24.12 5V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 443 24.13 3.3V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .444 24.14 Timer Interface Module Characteristics .
Table of Contents A.3 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .460 A.4 Low-Voltage Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 A.5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 A.5.1 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 461 A.5.2 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 461 A.5.3 5V Oscillator Characteristics . .
Data Sheet — MC68HC908LJ24 List of Figures Figure Title 1-1 1-2 1-3 1-4 MC68HC908LJ24 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 41 80-Pin QFP and LQFP Pin Assignment . . . . . . . . . . . . . . . . . . 42 64-pin QFP and LQFP Pin Assignment . . . . . . . . . . . . . . . . . . 43 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2-1 2-2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures Figure Title 8-5 8-6 8-7 8-8 8-9 8-10 PLL Bandwidth Control Register (PBWCR) . . . . . . . . . . . . . . 129 PLL Multiplier Select Register High (PMSH) . . . . . . . . . . . . . 130 PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . . . . 130 PLL VCO Range Select Register (PMRS) . . . . . . . . . . . . . . . 131 PLL Reference Divider Select Register (PMDS) . . . . . . . . . . 132 PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures Figure Title Page 10-7 10-8 10-9 10-10 Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . . 176 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .177 Data Block Format for ROM-Resident Routines. . . . . . . . . . . 180 EE_WRITE FLASH Memory Usage . . . . . . . . . . . . . . . . . . . .189 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures Figure Title 12-16 12-17 12-18 12-19 12-20 Day Register (DAYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Month Register (MTHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Year Register (YRR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Day-Of-Week Register (DOWR). . . . . . . . . . . . . . . . . . . . . . . 244 Chronograph Data Register (CHRR) . . . . . . . . . . . . . . . . . . .
List of Figures Figure Title Page 14-10 14-11 14-12 14-13 14-14 14-15 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . 302 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 305 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 312 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . . 314 SPI Data Register (SPDR) . . . . . . . . . . . . .
List of Figures Figure Title Page 17-11 1/4 Duty LCD Frontplane Driver Waveforms (continued) . . . . 364 17-12 7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . . . . 365 17-13 BP0–BP2 and FP0–FP2 Output Waveforms for 7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . . 366 17-14 "f" Segment Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . .367 17-15 "e" Segment Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . .
List of Figures Figure Title Page 19-3 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 406 20-1 20-2 20-3 20-4 KBI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .408 Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . 409 Keyboard Status and Control Register (KBSCR) . . . . . . . . . . 412 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . . 413 21-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures Data Sheet 32 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 List of Tables Table Title Page 2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 4-1 FLASH Block Protect Register to Physical Address . . . . . . . . . 78 5-1 LVI Trip Point Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6-1 6-2 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 10-14 10-15 10-16 10-17 10-18 Title Page MON_PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 MON_ERARNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 ICP_LDRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 EE_WRITE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 EE_READ Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11-1 Pin Name Conventions . . . . .
List of Tables Table Title Page 17-1 17-3 17-2 17-4 17-5 17-6 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 LCD Bias Voltage Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Resistor Ladder Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Fast Charge Duty Cycle Selection . . . . . . . . . . . . . . . . . . . . . 370 LCD Duty Cycle Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table A-1 A-2 A-3 A-4 A-5 Title 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 461 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 461 5V Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 462 3.3V Oscillator Specifications. . . . . . . . . . . . . . . . . . . . . . . . . 462 MC68HC908LK24 Order Numbers. . . . . . . . . . . . . . . . . . . . . 462 Data Sheet 36 Page MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.6 Pin Functions . . . . . . . . . . . . . .
General Description 1.2 Introduction The MC68HC908LJ24 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 1.
General Description Features – Temperature drift compensation by user software and external temperature sensor with temperature drift profile from crystal vendor • Serial communications interface module (SCI) with infrared (IR) encoder/decoder • Inter-IC Bus interface module (IIC) • Serial peripheral interface module (SPI) • IRQ external interrupt pin with integrated pullup • 8-bit keyboard wakeup port with programmable pullup • 4/3 backplanes and static with maximum 32/33 frontplanes liquid cry
General Description • Specific features of the MC68HC908LJ24 in 64-pin packages are: – 40 general-purpose I/Os only – High current 15-mA sink capability on 22 pins – 4/3 backplanes and static with maximum 26 or 27 frontplanes LCD driver Features of the CPU08 include the following: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the HC05) • 16-bit Index register and stack pointer • Memory-to-memory data transfers • Fast 8 × 8 multiply i
General Description MCU Block Diagram INTERNAL BUS CONTROL AND STATUS REGISTERS — 128 BYTES DDRA PORTA KEYBOARD INTERRUPT MODULE PORTB ARITHMETIC/LOGIC UNIT (ALU) PTB7/ADC5 PTB6/ADC4 PTB5/T2CH1† PTB4/T2CH0† PTB3/T1CH1† PTB2/T1CH0† PTB1/RxD† PTB0/TxD† PORTD CPU REGISTERS PTA7/ADC3 PTA6/ADC2 PTA5/ADC1 PTA4/ADC0 PTA3/KBI3** PTA2/KBI2** PTA1/KBI1** PTA0/KBI0** PTD7/KBI7/SDA PTD6/KBI6/SCL PTD5/KBI5/T2CLK** PTD4/KBI4/T1CLK** PTD3/SPSCK/CALOUT PTD2/MOSI PTD1/MISO PTD0/SS/CALIN PORTF M68HC08 CPU PTF7
General Description BP1 BP0 FP32 FP31 PTB5/T2CH1 PTB4/T2CH0 PTB3/T1CH1 PTB2/T1CH0 PTB1/RxD PTB0/TxD NC CGMXFC OSC2 OSC1 VSS VLCD VDD 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 FP0/BP3 1 61 VDDA BP2 79 80 PTD4/KBI4/T1CLK 1.
BP1 BP0 PTB5/T2CH1 PTB4/T2CH0 PTB3/T1CH1 PTB2/T1CH0 PTB1/RxD PTB0/TxD CGMXFC OSC2 OSC1 VSS VDD 62 61 60 59 58 57 56 55 54 53 52 51 50 FP0/BP3 1 49 VDDA BP2 63 64 PTD4/KBI4/T1CLK General Description Pin Assignments 48 VREFL PTD5/KBI5/T2CLK 2 47 VREFH FP1 3 46 PTB7/ADC5 FP2 4 45 PTB6/ADC4 FP3 5 PTF7 FP32 44 PTA7/ADC3 6 PTF6 FP31 43 PTA6/ADC2 PTF5 FP30 PTF4 FP29 42 PTA5/ADC1 PTF3 FP28 41 PTA4/ADC0 FP27 40 PTA3/KBI3 39 PTA2/KBI2 38 PTA1/
General Description 1.6 Pin Functions Description of pin functions are provided here. 1.6.1 Power Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-4 shows. Place the C1 bypass capacitor as close to the MCU as possible.
General Description Pin Functions 1.6.3 LCD Bias Voltage (VLCD) VLCD is the bias voltage supply for the LCD driver module. Connect the VLCD pin to the same voltage potential as VDD. For maximum noise immunity, route VLCD via a separate trace and place bypass capacitors as close as possible to the package. See Section 17. Liquid Crystal Display (LCD) Driver. 1.6.4 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit.
General Description 1.6.9 ADC Voltage Low Reference Pin (VREFL) VREFL is the voltage input pin for the ADC voltage low reference. See 16.7.5 ADC Voltage Reference Low Pin (VREFL). 1.6.10 Port A Input/Output (I/O) Pins (PTA7–PTA0) PTA7–PTA0 are special function, bidirectional port pins. See 18.3 Port A. PTA7/ADC3–PTA4/ADC0 are shared with ADC, and PTA3/KBI3–PTA0/KBI0 are shared with the KBI module. 1.6.
General Description Pin Functions 1.6.14 Port E I/O Pins (PTE7–PTE0) PTE7–PTE0 are special function, bidirectional port pins, with high current sink capability. See 18.7 Port E. PTE7/FP18–PTE0/FP11 are shared with the LCD frontplane drivers. 1.6.15 Port F I/O Pins (PTF7–PTF0) PTF7–PTF0 are general purpose bidirectional port pins with high current sink capability. See 18.8 Port F. 1.6.
General Description Data Sheet 48 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 2. Memory Map 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 49 2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.2 Introduction The CPU08 can address 64k-bytes of memory space.
Memory Map 2.4 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-2 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R. 2.5 Input/Output (I/O) Section Most of the control, status, and data registers are in the zero page $0000–$007F.
Memory Map Input/Output (I/O) Section $0000 ↓ $007F I/O Registers 128 Bytes $0080 ↓ $037F RAM 768 Bytes $0380 ↓ $8FFF Unimplemented 35,968 Bytes $9000 ↓ $EFFF User FLASH Memory 24,576 Bytes $F000 ↓ $FBFF Unimplemented 3,072 Bytes $FC00 ↓ $FDFF Monitor ROM 1 512 Bytes $FE00 SIM Break Status Register (SBSR) $FE01 SIM Reset Status Register (SRSR) $FE02 Reserved $FE03 SIM Break Flag Control Register (SBFCR) $FE04 Interrupt Status Register 1 (INT1) $FE05 Interrupt Status Register 2 (INT2)
Memory Map Addr.
Memory Map Input/Output (I/O) Section Addr.
Memory Map Addr.
Memory Map Input/Output (I/O) Section Addr. $001E $001F Register Name Read: IRQ Status and Control Register Write: (INTSCR) Reset: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 IRQF 0 IMASK MODE 0 0 0 SSREC STOP COPD 0 0 0 PS2 PS1 PS0 ACK 0 Read: COPRS Configuration Register 1 Write: † (CONFIG1) Reset: 0 0 0 0 LVISTOP LVIRSTD LVIPWRD 0 0 TOIE TSTOP 0 0 0†† 0 0 0 † One-time writable register after each reset. †† Reset by POR only.
Memory Map Addr.
Memory Map Input/Output (I/O) Section Addr.
Memory Map Addr.
Memory Map Input/Output (I/O) Section Addr.
Memory Map Addr.
Memory Map Input/Output (I/O) Section Addr.
Memory Map Addr.
Memory Map Input/Output (I/O) Section Addr. Register Name Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Bit 7 6 5 4 3 2 R R R R R R 1 Bit 0 SBSW R Note 0 Note: Writing a logic 0 clears SBSW.
Memory Map Addr.
Memory Map Input/Output (I/O) Section . Table 2-1. Vector Addresses Priority Lowest INT Flag IF18 IF17 IF16 IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 IF6 IF5 IF4 IF3 IF2 IF1 — Highest — Address $FFD8 $FFD9 $FFDA $FFDB $FFDC $FFDD $FFDE $FFDF $FFE0 $FFE1 $FFE2 $FFE3 $FFE4 $FFE5 $FFE6 $FFE7 $FFE8 $FFE9 $FFEA $FFEB $FFEC $FFED $FFEE $FFEF $FFF0 $FFF1 $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF MC68HC908LJ24/LK24 — Rev. 2.
Memory Map Data Sheet 66 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 3. Random-Access Memory (RAM) 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 3.2 Introduction This section describes the 768 bytes of RAM (random-access memory). 3.3 Functional Description Addresses $0080 through $037F are RAM locations. The location of the stack RAM is programmable.
Random-Access Memory (RAM) During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Data Sheet 68 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 4. FLASH Memory (FLASH) 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . .
FLASH Memory (FLASH) Addr. $FE08 Register Name Bit 7 6 5 4 0 0 0 0 0 0 0 BPR7 BPR6 BPR5 Read: FLASH Control Register Write: (FLCR) Reset: $FFCF Read: FLASH Block Protect Register Write: (FLBPR)# Reset: 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 0 BPR4 BPR3 BPR2 BPR1 BPR0 Unaffected by reset; $FF when blank # Non-volatile FLASH register; write by programming. = Unimplemented Figure 4-1. FLASH I/O Register Summary 4.
FLASH Memory (FLASH) FLASH Control Register 4.4 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations. Address: Read: $FE08 Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 Figure 4-2. FLASH Control Register (FLCR) HVEN — High Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array.
FLASH Memory (FLASH) 4.5 FLASH Page Erase Operation Use the following procedure to erase a page of FLASH memory. A page consists of 128 consecutive bytes starting from addresses $xx00 or $xx80. The 48-byte user interrupt vectors area also forms a page. The 48-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. Mass erase is required to erase this page. 1. Set the ERASE bit and clear the MASS bit in the FLASH control register. 2.
FLASH Memory (FLASH) FLASH Mass Erase Operation 4.6 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address within the FLASH memory address range. 4. Wait for a time, tnvs (10µs). 5. Set the HVEN bit. 6. Wait for a time tmerase (4ms). 7. Clear the ERASE bit. 8. Wait for a time, tnvh1 (100µs). 9. Clear the HVEN bit. 10.
FLASH Memory (FLASH) 4.7 FLASH Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes starting from addresses $xx00, $xx40, $xx80, or $xxC0. Use the following procedure to program a row of FLASH memory. (Figure 4-3 shows a flowchart of the programming algorithm.) 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read the FLASH block protect register. 3.
FLASH Memory (FLASH) FLASH Program Operation Algorithm for programming a row (64 bytes) of FLASH memory 1 Set PGM bit 2 Read the FLASH block protect register 3 Write any data to any FLASH location within the address range of the row to be programmed 4 Wait for a time, tnvs 5 Set HVEN bit 6 Wait for a time, tpgs 7 8 Write data to the FLASH address to be programmed Wait for a time, tprog Completed programming this row? Y N NOTE: The time between each FLASH address change (step 7 to step 7
FLASH Memory (FLASH) 4.8 FLASH Block Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect pages of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected.
FLASH Memory (FLASH) FLASH Block Protection 4.8.1 FLASH Block Protect Register The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting location of the protected range within the FLASH memory.
FLASH Memory (FLASH) Table 4-1. FLASH Block Protect Register to Physical Address BPR[7:0] Start Address of Protection Range(1) $00 to $1F The entire FLASH memory is NOT protected.(2) $20 $9000 (1001 0000 0000 0000) The entire FLASH memory is protected. $21 $9080 (1001 0000 1000 0000) $22 $9100 (1001 0001 0000 0000) $23 $9180 (1001 0001 1000 0000) $24 $9200 (1001 0010 0000 0000) and so on...
Data Sheet — MC68HC908LJ24 Section 5. Configuration Registers (CONFIG) 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 5.4 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . . 81 5.5 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . . 82 5.
Configuration Registers (CONFIG) Addr. $001D $001F Register Name Read: Configuration Register 2 Write: (CONFIG2)† Reset: Bit 7 6 PEE STOP_ IRCDIS 0 0 Read: COPRS Configuration Register 1 † Write: (CONFIG1) Reset: 0 5 4 STOP_ DIV2CLK XCLKEN 0 0 LVISTOP LVIRSTD LVIPWRD 0 0 0†† 3 2 1 Bit 0 PCEH PCEL LVISEL1 LVISEL0 0 0 0†† 1†† SSREC STOP COPD 0 0 0 0 0 † One-time writable register after each reset. †† Reset by POR only. = Unimplemented Figure 5-1.
Configuration Registers (CONFIG) Configuration Register 1 (CONFIG1) 5.4 Configuration Register 1 (CONFIG1) The CONFIG1 register can be written once after each reset. Address: $001F Bit 7 Read: Write: Reset: COPRS 0 6 5 4 LVISTOP LVIRSTD LVIPWRD 0 0 †† Reset by POR only. 0†† 3 0 0 2 1 Bit 0 SSREC STOP COPD 0 0 0 = Unimplemented Figure 5-2. Configuration Register 1 (CONFIG1) COPRS — COP Rate Select COPRS selects the COP time-out period. Reset clears COPRS. (See Section 21.
Configuration Registers (CONFIG) SSREC — Short Stop Recovery SSREC enables the CPU to exit stop mode with a delay of 32 ICLK cycles instead of a 4096 ICLK cycle delay. 1 = Stop mode recovery after 32 ICLK cycles 0 = Stop mode recovery after 4096 ICLK cycles NOTE: Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal oscillator, do not set the SSREC bit.
Configuration Registers (CONFIG) Configuration Register 2 (CONFIG2) PEE — Port E Enable Setting PEE configures the PTE0/FP11–PTE7/FP18 pins for LCD frontplane driver use. Reset clears this bit. 1 = PTE0/FP11–PTE7/FP18 pins configured as LCD frontplane driver pins: FP11–FP18 0 = PTE0/FP11–PTE7/FP18 pins configured as standard I/O pins: PTE0–PTE7 STOP_IRCDIS — Internal RC Oscillator Stop Mode Disable Setting STOP_IRCDIS disables the internal RC oscillator during stop mode.
Configuration Registers (CONFIG) PCEH — Port C Enable High Nibble Setting PCEH configures the PTC4/FP23–PTC7/FP26 pins for LCD frontplane driver use. Reset clears this bit. 1 = PTC4/FP23–PTC7/FP26 pins configured as LCD frontplane driver pins: FP23–FP26 0 = PTC4/FP23–PTC7/FP26 pins configured as standard I/O pins: PTC4–PTC7 PCEL — Port C Enable Low Nibble Setting PCEL configures the PTC0/FP19–PTC3/FP22 pins for LCD frontplane driver use. Reset clears this bit.
Data Sheet — MC68HC908LJ24 Section 6. Central Processor Unit (CPU) 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.4.2 Index Register . . . . . . . .
Central Processor Unit (CPU) 6.2 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 6.
Central Processor Unit (CPU) CPU Registers 6.4 CPU Registers Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map. 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 6-1. CPU Registers 6.4.1 Accumulator The accumulator is a general-purpose 8-bit register.
Central Processor Unit (CPU) 6.4.2 Index Register The 16-bit index register allows indexed addressing of a 64K-byte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
Central Processor Unit (CPU) CPU Registers NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations. 6.4.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched.
Central Processor Unit (CPU) 6.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 6-6.
Central Processor Unit (CPU) CPU Registers I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
Central Processor Unit (CPU) C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 6.5 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set.
Central Processor Unit (CPU) CPU During Break Interrupts 6.6.2 Stop Mode The STOP instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock. After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. 6.
Central Processor Unit (CPU) V H I N Z C ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP A ← (A) + (M) + (C) Add with Carry IMM DIR EXT IX2 R R – R R R IX1 IX SP1 SP2 A9 B9 C9 D9 E9 F9 9EE9 9ED9 ii dd hh ll ee ff ff IMM DIR EXT IX2 R R – R R R IX1 IX SP1 SP2 AB BB CB DB EB FB 9EEB 9EDB ii dd hh ll ee ff ff ff ee ff A7 ii 2 – – – – – – IMM AF ii 2 IMM DIR EXT IX2 0 – – R R – IX1 IX SP1 SP2 A4 B4 C4 D4 E4 F4 9EE4 9ED4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 DIR INH
Central Processor Unit (CPU) Opcode Map Effect on CCR V H I N Z C Cycles Description Operand Operation Opcode Source Form Address Mode Table 6-1.
Central Processor Unit (CPU) Table 6-1.
Central Processor Unit (CPU) Opcode Map Effect on CCR V H I N Z C CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Compare A with M (A) – (M) COM opr COMA COMX COM opr,X COM ,X COM opr,SP Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M
Central Processor Unit (CPU) V H I N Z C INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Load A from M LDHX #opr LDHX opr Load H:X from M LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP DIR INH INH R – – R R – IX1 IX SP1 3C 4C 5C 6C 7C 9E6C PC ← Jump Address DIR EXT – – – – – – IX2 IX1 IX BC CC DC EC FC dd hh ll ee ff ff 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (P
Central Processor Unit (CPU) Opcode Map Table 6-1.
Central Processor Unit (CPU) Effect on CCR V H I N Z C RTI Return from Interrupt RTS Return from Subroutine Cycles Description Operand Operation Opcode Source Form Address Mode Table 6-1.
Central Processor Unit (CPU) Opcode Map V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 6-1.
MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
Data Sheet — MC68HC908LJ24 Section 7. Oscillator (OSC) 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.3 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.4 X-tal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.5.1 Crystal Amplifier Input Pin (OSC1). . .
Oscillator (OSC) The reference clock for the CGM, real time clock module (RTC) and other MCU sub-systems is driven by the crystal oscillator. The COP module is always driven by internal RC clock. The internal RC oscillator runs continuously after a POR or reset and is always available in run and wait modes. In stop mode, it can be disabled by setting the STOP_IRCDIS bit in CONFIG2 register. Figure 7-1. shows the block diagram of the oscillator module.
Oscillator (OSC) Internal Oscillator 7.3 Internal Oscillator The internal RC oscillator clock (ICLK) is a free running 64kHz clock (at VDD = 5V) that requires no external components. It is the reference clock input to the computer operating properly (COP) module. The ICLK can be turned off in stop mode by setting the STOP_IRCDIS bit in CONFIG2. After reset, the bit is clear by default and ICLK is enabled during stop mode. 7.
Oscillator (OSC) 7.5.1 Crystal Amplifier Input Pin (OSC1) OSC1 pin is an input to the crystal oscillator amplifier. Schmitt trigger and glitch filter are implemented on this pin to improve EMC performance. See Section 24. Electrical Specifications for detail specification of the glitch filter. 7.5.2 Crystal Amplifier Output Pin (OSC2) OSC2 pin is the output of the crystal oscillator inverting amplifier. 7.5.
Oscillator (OSC) Oscillator During Break Mode 7.6.1 Wait Mode The WAIT instruction has no effect on the oscillator module. CGMXCLK, CGMRCLK, and ICLK continues to drive the MCU modules. 7.6.2 Stop Mode The STOP instruction clears the SIMOSCEN signal, and hence the CGMXCLK (and CGMRCLK) clock stops running. For continuous CGMXCLK operation in stop mode, set the STOP_XCLKEN to logic 1 before entering stop mode.
Oscillator (OSC) Data Sheet 108 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 8. Clock Generator Module (CGM) 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.4.1 Oscillator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.2 Phase-Locked Loop Circuit (PLL) . . . .
Clock Generator Module (CGM) 8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 8.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 8.8.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . 134 8.
Clock Generator Module (CGM) Features 8.
Clock Generator Module (CGM) OSCILLATOR (OSC) MODULE See Section 7. Oscillator (OSC).
Clock Generator Module (CGM) Functional Description Addr.
Clock Generator Module (CGM) 8.4.1 Oscillator Module The oscillator module provides two clock outputs CGMXCLK and CGMRCLK to the CGM module. CGMXCLK or CGMXCLK divide-by-two can be selected to drive the SIM module to generate the system bus clocks. CGMRCLK is the reference clock for the phase-lock-loop, to generate a higher frequency clock. The oscillator module also provides the reference clock for the real time clock (RTC) module. See Section 7.
Clock Generator Module (CGM) Functional Description The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the CGMXFC pin changes the frequency within this range. By design, fVRS is equal to the nominal center-of-range frequency, fNOM, (38.
Clock Generator Module (CGM) 8.4.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control register. (See 8.6.
Clock Generator Module (CGM) Functional Description The following conditions apply when the PLL is in automatic bandwidth control mode: • The ACQ bit (See 8.6.2 PLL Bandwidth Control Register.) is a read-only indicator of the mode of the filter. (See 8.4.4 Acquisition and Tracking Modes.) • The ACQ bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance. (See 8.9 Acquisition/Lock Time Specifications for more information.
Clock Generator Module (CGM) The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. • Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (See 8.9 Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL control register (PCTL).
Clock Generator Module (CGM) Functional Description The relationship between the VCO frequency, fVCLK, and the reference frequency, fRCLK, is P 2 N f VCLK = ----------- ( f RCLK ) R where N is the integer range multiplier, between 1 and 4095. In cases where desired bus frequency has some tolerance, choose fRCLK to a value determined either by other module requirements (such as modules which are clocked by CGMXCLK), cost requirements, or ideally, as high as the specified range allows. See Section 24.
Clock Generator Module (CGM) 6. Select the VCO’s power-of-two range multiplier E, according to this table: Frequency Range E 0 < fVCLK < 9,830,400 0 9,830,400 ≤ fVCLK < 19,660,800 1 19,660,800 ≤ fVCLK < 39,321,600 2 NOTE: Do not program E to a value of 3. 7. Select a VCO linear range multiplier, L, where fNOM = 38.4kHz f VCLK L = round -------------------------- 2E × f NOM 8. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, fVRS.
Clock Generator Module (CGM) Functional Description 10. Program the PLL registers accordingly: a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P. b. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E. c. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N. d. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L. e.
Clock Generator Module (CGM) 8.4.7 Special Programming Exceptions The programming method described in 8.4.6 Programming the PLL does not account for three possible exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for these exceptions: • A 0 value for R or N is interpreted exactly the same as a value of 1. • A 0 value for L disables the PLL and prevents its selection as the source for the base clock. (See 8.4.8 Base Clock Selector Circuit.) 8.4.
Clock Generator Module (CGM) I/O Signals 8.4.9 CGM External Connections In its typical configuration, the CGM requires up to four external components. Figure 8-3 shows the external components for the PLL: • Bypass capacitor, CBYP • Filter network Care should be taken with PCB routing in order to minimize signal cross talk and noise. (See 8.9 Acquisition/Lock Time Specifications for routing information, filter network and its effects on PLL performance.) MCU VSSA CGMXFC VDDA VDD 10 kΩ 0.
Clock Generator Module (CGM) 8.5.1 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure 8-3.) NOTE: To prevent noise problems, the filter network should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the network. 8.5.2 PLL Analog Power Pin (VDDA) VDDA is a power pin used by the analog portions of the PLL.
Clock Generator Module (CGM) CGM Registers 8.5.6 CGM VCO Clock Output (CGMVCLK) CGMVCLK is the clock output from the VCO. 8.5.7 CGM Base Clock Output (CGMOUT) CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be equal to CGMXCLK, CGMXCLK divided by two, or CGMPCLK divided by two. 8.5.
Clock Generator Module (CGM) 8.6.1 PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits. Address: $0036 Bit 7 Read: Write: Reset: PLLIE 0 6 PLLF 0 5 4 3 2 1 Bit 0 PLLON BCS PRE1 PRE0 VPR1 VPR0 1 0 0 0 0 0 = Unimplemented Figure 8-4.
Clock Generator Module (CGM) CGM Registers PLLON — PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 8.4.8 Base Clock Selector Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
Clock Generator Module (CGM) Table 8-2. PRE 1 and PRE0 Programming PRE1 and PRE0 P Prescaler Multiplier 00 0 1 01 1 2 10 2 4 11 3 8 VPR1 and VPR0 — VCO Power-of-Two Range Select Bits These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction with L (See 8.4.3 PLL Circuits, 8.4.6 Programming the PLL, and 8.6.4 PLL VCO Range Select Register.) controls the hardware center-of-range frequency, fVRS. VPR1:VPR0 cannot be written when the PLLON bit is set.
Clock Generator Module (CGM) CGM Registers Address: $0037 Bit 7 Read: AUTO Write: Reset: 0 6 LOCK 0 5 ACQ 0 4 3 2 1 0 0 0 0 0 0 0 0 = Unimplemented R Bit 0 R 0 = Reserved Figure 8-5. PLL Bandwidth Control Register (PBWCR) AUTO — Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.
Clock Generator Module (CGM) 8.6.3 PLL Multiplier Select Registers The PLL multiplier select registers (PMSH and PMSL) contain the programming information for the modulo feedback divider. Address: Read: $0038 Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 MUL11 MUL10 MUL9 MUL8 0 0 0 0 = Unimplemented Figure 8-6.
Clock Generator Module (CGM) CGM Registers 8.6.4 PLL VCO Range Select Register The PLL VCO range select register (PMRS) contains the programming information required for the hardware configuration of the VCO. Address: Read: Write: Reset: $003A Bit 7 6 5 4 3 2 1 Bit 0 VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0 0 1 0 0 0 0 0 0 Figure 8-8.
Clock Generator Module (CGM) 8.6.5 PLL Reference Divider Select Register The PLL reference divider select register (PMDS) contains the programming information for the modulo reference divider. Address: Read: $003B Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 RDS3 RDS2 RDS1 RDS0 0 0 0 1 = Unimplemented Figure 8-9.
Clock Generator Module (CGM) Interrupts 8.7 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as logic 0.
Clock Generator Module (CGM) 8.8.2 Stop Mode If the oscillator stop mode enable bit (STOP_XCLKEN in CONFIG2 register) is configured to disabled the oscillator in stop mode, then the STOP instruction disables the CGM (oscillator and phase locked loop) and holds low all CGM outputs (CGMOUT, CGMVCLK, CGMPCLK, and CGMINT).
Clock Generator Module (CGM) Acquisition/Lock Time Specifications 8.9 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 8.9.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input.
Clock Generator Module (CGM) The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV. This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections.
Clock Generator Module (CGM) Acquisition/Lock Time Specifications 8.9.3 Choosing a Filter As described in 8.9.2 Parametric Influences on Reaction Time, the external filter network is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. Either of the filter networks in Figure 8-10 is recommended when using a 32.768kHz reference clock (CGMRCLK). Figure 8-10 (a) is used for applications requiring better stability.
Clock Generator Module (CGM) Data Sheet 138 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 9. System Integration Module (SIM) 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 142 9.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.3.2 Clock Start-up from POR or LVI Reset. . . . . . . . . . . . . . . . 143 9.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . .
System Integration Module (SIM) 9.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 156 9.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 9.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9.8.
System Integration Module (SIM) Introduction MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO CGM, OSC) SIM COUNTER COP CLOCK ICLK (FROM OSC) CGMOUT (FROM CGM) ÷2 CLOCK CONTROL VDD CLOCK GENERATORS INTERNAL CLOCKS INTERNAL PULLUP DEVICE LVI (FROM LVI MODULE) RESET PIN LOGIC POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) RESET
System Integration Module (SIM) Addr. Register Name Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Bit 7 6 5 4 3 2 R R R R R R 1 SBSW Note Bit 0 R 0 Note: Writing a logic 0 clears SBSW.
System Integration Module (SIM) SIM Bus Clock Control and Generation OSC2 OSCILLATOR (OSC) MODULE CGMXCLK OSC1 ICLK STOP MODE CLOCK ENABLE SIGNALS FROM CONFIG2 TO RTC, ADC SIM COUNTER SIMOSCEN SYSTEM INTEGRATION MODULE CGMRCLK CGMOUT ÷2 PHASE-LOCKED LOOP (PLL) SIMDIV2 BUS CLOCK GENERATORS IT12 TO REST OF MCU IT23 TO REST OF MCU PTC1 MONITOR MODE USER MODE Figure 9-3. CGM Clock Signals 9.3.
System Integration Module (SIM) 9.3.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt, break, or reset, the SIM allows ICLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 ICLK cycles. (See 9.7.2 Stop Mode.) In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
System Integration Module (SIM) Reset and System Initialization 9.4.1 External Pin Reset The RST pin circuit includes an internal pull-up device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 ICLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 9-2 for details. Figure 9-4 shows the relative timing. Table 9-2.
System Integration Module (SIM) IRST RST RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES ICLK IAB VECTOR HIGH Figure 9-5. Internal Reset Timing The COP reset is asynchronous to the bus clock. ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR INTERNAL RESET Figure 9-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 9.4.2.
System Integration Module (SIM) Reset and System Initialization OSC1 PORRST 4096 CYCLES 32 CYCLES 32 CYCLES ICLK CGMOUT RST IRST $FFFE IAB $FFFF Figure 9-7. POR Recovery 9.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources.
System Integration Module (SIM) 9.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 9.4.2.
System Integration Module (SIM) SIM Counter 9.5 SIM Counter The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the clock for the COP module. The SIM counter is 12 bits long and is clocked by the falling edge of ICLK. 9.5.
System Integration Module (SIM) 9.6 Exception Control Normal, sequential program execution can be changed in three different ways: • Interrupts: – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) • Reset • Break interrupts 9.6.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts.
System Integration Module (SIM) Exception Control Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). (See Figure 9-10.
System Integration Module (SIM) 9.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts.
System Integration Module (SIM) Exception Control 9.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. 9.6.1.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources.
System Integration Module (SIM) Table 9-3.
System Integration Module (SIM) Exception Control 9.6.1.5 Interrupt Status Register 2 Address: $FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 9-13. Interrupt Status Register 2 (INT2) IF14–IF7 — Interrupt Flags 14–7 These flags indicate the presence of interrupt requests from the sources shown in Table 9-3. 1 = Interrupt request present 0 = No interrupt request present 9.6.1.
System Integration Module (SIM) 9.6.2 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 9.6.3 Break Interrupts The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. (See Section 23. Break Module (BRK).) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. 9.
System Integration Module (SIM) Low-Power Modes 9.7 Low-Power Modes Executing the WAIT or STOP instruction puts the MCU in a low powerconsumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 9.7.
System Integration Module (SIM) IAB $6E0B IDB $A6 $6E0C $A6 $A6 $00FF $01 $0B $00FE $00FD $00FC $6E EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt Figure 9-16. Wait Recovery from Interrupt or Break 32 CYCLES IAB IDB 32 CYCLES $6E0B $A6 $A6 RST VCT H RST VCT L $A6 RST ICLK Figure 9-17. Wait Recovery from Internal Reset 9.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled.
System Integration Module (SIM) SIM Registers A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status register (SBSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 9-18 shows stop mode entry timing. NOTE: To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
System Integration Module (SIM) 9.8.1 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop mode or wait mode. Address: Read: Write: $FE00 Bit 7 6 5 4 3 2 R R R R R R Reset: 1 SBSW Note Bit 0 R 0 Note: Writing a logic 0 clears SBSW. R = Reserved Figure 9-20. SIM Break Status Register (SBSR) SBSW — Break Wait Bit This status bit is set when a break interrupt causes an exit from wait mode or stop mode.
System Integration Module (SIM) SIM Registers 9.8.2 SIM Reset Status Register This register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register. Address: Read: $FE01 Bit 7 6 5 4 3 2 1 Bit 0 POR PIN COP ILOP ILAD 0 LVI 0 1 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 9-21.
System Integration Module (SIM) 9.8.3 SIM Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state. Address: Read: Write: Reset: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 9-22.
Data Sheet — MC68HC908LJ24 Section 10. Monitor ROM (MON) 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10.4.2 Data Format . . . . . . . . . . . . . . . . . .
Monitor ROM (MON) 10.2 Introduction This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
Monitor ROM (MON) Functional Description 10.4 Functional Description The monitor ROM receives and executes commands from a host computer. Figure 10-1 shows an example circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions.
Monitor ROM (MON) RST 0.1 µF HC908LJ24 VDD VDD VDDA VLCD 0.1 µF VREFH VDD VSS VREFL 4.9152MHz/9.8304MHz (50% DUTY) CGMXFC OSC1 0.01 µF 10k 0.033 µF MUST BE USED IF SW2 IS AT POSITION C. CONNECT TO OSC1, WITH OSC2 UNCONNECTED. EXT OSC 32.768kHz 6–30 pF MAX232 1 1 µF + 3 4 1 µF + C1+ C1– GND C2+ V+ 5 C2– V– OSC2 16 6–30 pF + 1 µF 15 + 1 µF XTAL CIRCUIT VDD 6 + 2 7 10 3 8 9 C VTST 2 DB9 5 330k VDD VCC 10M OSC1 1 µF 1k 8.
Monitor ROM (MON) Functional Description 10.4.1 Entering Monitor Mode Table 10-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. If $FFFE and $FFFF do not contain $FF (programmed state): – The external clock is 4.9152 MHz with PTC1 low or 9.8304 MHz with PTC1 high – IRQ = VTST (PLL off) 2.
Monitor ROM (MON) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor IRQ RST Address $FFFE/ $FFFF PTA2 PTA1 PTA0(1) PTC1 External Clock(2) Bus Frequency PLL COP Baud Rate X GND X X X X X X 0 X Disabled 0 No operation until reset goes high VTST(3) VDD or VTST X 0 1 1 0 4.9152 MHz 2.4576 MHz OFF Disabled 9600 PTA1 and PTA2 voltages only required if IRQ = VTST; PTC1 determines frequency divider VTST(3) VDD or VTST X 0 1 1 1 9.8304 MHz 2.
Monitor ROM (MON) Functional Description NOTE: If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial POR reset. Once the part has been programmed, the traditional method of applying a voltage, VTST, to IRQ must be used to enter monitor mode.
Monitor ROM (MON) POR RESET IS VECTOR BLANK? NO NORMAL USER MODE YES MONITOR MODE EXECUTE MONITOR CODE POR TRIGGERED? NO YES Figure 10-2. Low-Voltage Monitor Mode Entry Flowchart In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code.
Monitor ROM (MON) Functional Description 10.4.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 NEXT START STOP BIT BIT BIT 7 Figure 10-3. Monitor Data Format 10.4.3 Break Signal A start bit (logic 0) followed by nine logic 0 bits is a break signal.
Monitor ROM (MON) Table 10-3 lists external frequencies required to achieve a standard baud rate of 9600 BPS. Other standard baud rates can be accomplished using proportionally higher or lower frequency generators. If using a crystal as the clock source, be aware of the upper frequency limit that the internal clock module can handle. Table 10-3. Monitor Baud Rate Selection External Frequency IRQ PTC1 Internal Frequency Baud Rate (BPS) 4.9152 MHz VTST 0 2.4576 MHz 9600 9.8304 MHz VTST 1 2.
Monitor ROM (MON) Functional Description FROM HOST 4 ADDRESS HIGH READ READ 4 1 ADDRESS HIGH ADDRESS LOW 1 4 ADDRESS LOW DATA 1 3, 2 4 ECHO RETURN Notes: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte. Figure 10-5.
Monitor ROM (MON) Table 10-5. WRITE (Write Memory) Command Description Write byte to memory Operand 2-byte address in high-byte:low-byte order; low byte followed by data byte Data Returned None Opcode $49 Command Sequence FROM HOST WRITE ADDRESS HIGH WRITE ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 10-6.
Monitor ROM (MON) Functional Description Table 10-7. IWRITE (Indexed Write) Command Description Write to last address accessed + 1 Operand Single data byte Data Returned None Opcode $19 Command Sequence FROM HOST IWRITE IWRITE DATA DATA ECHO A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 10-8.
Monitor ROM (MON) Table 10-9. RUN (Run User Program) Command Description Executes PULH and RTI instructions Operand None Data Returned None Opcode $28 Command Sequence FROM HOST RUN RUN ECHO The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program.
Monitor ROM (MON) Security 10.5 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain userdefined data. NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors.
Monitor ROM (MON) Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command.
Monitor ROM (MON) ROM-Resident Routines 10.6 ROM-Resident Routines Eight routines stored in the monitor ROM area (thus ROM-resident) are provided for FLASH memory manipulation. Six of the eight routines are intended to simplify FLASH program, erase, and load operations. The other two routines are intended to simplify the use of the FLASH memory as EEPROM. Table 10-10 shows a summary of the ROM-resident routines. Table 10-10.
Monitor ROM (MON) R FILE_PTR $XXXX A M BUS SPEED (BUS_SPD) ADDRESS AS POINTER DATA SIZE (DATASIZE) START ADDRESS HIGH (ADDRH) START ADDRESS LOW (ADDRL) DATA 0 DATA 1 DATA BLOCK DATA ARRAY DATA N Figure 10-9. Data Block Format for ROM-Resident Routines The control and data bytes are described below. • Bus speed — This one byte indicates the operating bus speed of the MCU. The value of this byte should be equal to 4 times the bus speed. E.g., for a 4MHz bus, the value is 16 ($10).
Monitor ROM (MON) ROM-Resident Routines 10.6.1 PRGRNGE PRGRNGE is used to program a range of FLASH locations with data loaded into the data array. Table 10-11.
Monitor ROM (MON) ORG RAM : FILE_PTR: BUS_SPD DATASIZE START_ADDR DATAARRAY DS.B DS.B DS.W DS.B 1 1 1 64 PRGRNGE FLASH_START EQU EQU $FC06 $EF00 ; ; ; ; Indicates 4x bus frequency Data size to be programmed FLASH start address Reserved data array ORG FLASH INITIALISATION: MOV #20, BUS_SPD MOV #64, DATASIZE LDHX #FLASH_START STHX START_ADDR RTS MAIN: BSR INITIALISATION : : LDHX #FILE_PTR JSR PRGRNGE Data Sheet 182 MC68HC908LJ24/LK24 — Rev. 2.
Monitor ROM (MON) ROM-Resident Routines 10.6.2 ERARNGE ERARNGE is used to erase a range of locations in FLASH. Table 10-12. ERARNGE Routine Routine Name ERARNGE Routine Description Erase a page or the entire array Calling Address $FCBE Stack Used 9 bytes Data Block Format Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) There are two sizes of erase ranges: a page or the entire array.
Monitor ROM (MON) 10.6.3 LDRNGE LDRNGE is used to load the data array in RAM with data from a range of FLASH locations. Table 10-13.
Monitor ROM (MON) ROM-Resident Routines 10.6.4 MON_PRGRNGE In monitor mode, MON_PRGRNGE is used to program a range of FLASH locations with data loaded into the data array. Table 10-14.
Monitor ROM (MON) 10.6.5 MON_ERARNGE In monitor mode, ERARNGE is used to erase a range of locations in FLASH. Table 10-15. MON_ERARNGE Routine Routine Name MON_ERARNGE Routine Description Erase a page or the entire array, in monitor mode Calling Address $FF2C Stack Used 11 bytes Data Block Format Bus speed Data size Starting address (high byte) Starting address (low byte) The MON_ERARNGE routine is designed to be used in monitor mode. It performs the same function as the ERARNGE routine (see 10.6.
Monitor ROM (MON) ROM-Resident Routines 10.6.6 MON_LDRNGE In monitor mode, LDRNGE is used to load the data array in RAM with data from a range of FLASH locations. Table 10-16.
Monitor ROM (MON) 10.6.7 EE_WRITE EE_WRITE is used to write a set of data from the data array to FLASH. Table 10-17. EE_WRITE Routine Routine Name EE_WRITE Routine Description Emulated EEPROM write. Data size ranges from 2 to 15 bytes at a time. Calling Address $FC00 Stack Used 17 bytes Data Block Format Bus speed (BUS_SPD) Data size (DATASIZE)(1) Starting address (ADDRH)(2) Starting address (ADDRL)(1) Data 1 : Data N Notes: 1. The minimum data size is 2 bytes. The maximum data size is 15 bytes.
Monitor ROM (MON) ROM-Resident Routines When the user dedicates a page of FLASH for data storage, and the size of the data array defined, each call of the EE_WRTIE routine will automatically transfer the data in the data array (in RAM) to the next blank block of locations in the FLASH page. Once a page is filled up, the EE_WRITE routine automatically erases the page, and starts reuse the page again. In the 128-byte page, an 8-byte control block is used by the routine to monitor the utilization of the page.
Monitor ROM (MON) ORG RAM : FILE_PTR: BUS_SPD DATASIZE START_ADDR DATAARRAY DS.B DS.B DS.W DS.
Monitor ROM (MON) ROM-Resident Routines 10.6.8 EE_READ EE_READ is used to load the data array in RAM with a set of data from FLASH. Table 10-18. EE_READ Routine Routine Name EE_READ Routine Description Emulated EEPROM read. Data size ranges from 2 to 15 bytes at a time. Calling Address $FC03 Stack Used 15 bytes Data Block Format Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH)(1) Starting address (ADDRL)(1) Data 1 : Data N Notes: 1.
Monitor ROM (MON) NOTE: The EE_READ routine is unable to check for incorrect data blocks, such as the FLASH page boundary address and data size. It is the responsibility of the user to ensure the starting address indicated in the data block is at the FLASH page boundary and the data size is 2 to 15. If the FLASH page is programmed with a data array with a different size, the EE_READ call will be ignored. Data Sheet 192 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 11. Timer Interface Module (TIM) 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 11.5.1 TIM Counter Prescaler . . . . . .
Timer Interface Module (TIM) 11.2 Introduction This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 11-1 is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2. 11.
Timer Interface Module (TIM) Pin Name Conventions 11.4 Pin Name Conventions The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are T[1,2]CH0 (timer channel 0). T[1,2]CH1 (timer channel 1), and T[1,2]CLK (external timer clock), where “1” is used to indicate TIM1 and “2” is used to indicate TIM2. The full names of the TIM I/O pins are listed in Table 11-1. The generic pin names appear in the text that follows. Table 11-1.
Timer Interface Module (TIM) T[1,2]CLK PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TOIE 16-BIT COMPARATOR INTERRUPT LOGIC TMODH:TMODL TOV0 ELS0B CHANNEL 0 ELS0A CH0MAX 16-BIT COMPARATOR TCH0H:TCH0L PORT LOGIC T[1,2]CH0 CH0F 16-BIT LATCH CH0IE MS0A INTERRUPT LOGIC MS0B INTERNAL BUS TOV1 ELS1B CHANNEL 1 ELS1A CH1MAX 16-BIT COMPARATOR TCH1H:TCH1L PORT LOGIC T[1,2]CH1 CH1F 16-BIT LATCH MS1A CH1IE INTERRUPT LOGIC Figure 11-1.
Timer Interface Module (TIM) Functional Description Addr.
Timer Interface Module (TIM) Addr.
Timer Interface Module (TIM) Functional Description Addr.
Timer Interface Module (TIM) 11.5.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. 11.5.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 11.5.
Timer Interface Module (TIM) Functional Description 11.5.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin.
Timer Interface Module (TIM) The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000. See 11.10.1 TIM Status and Control Register.
Timer Interface Module (TIM) Functional Description Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: NOTE: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value.
Timer Interface Module (TIM) NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 11.5.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1.
Timer Interface Module (TIM) Interrupts Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM channel 0 status and control register (TSC0) controls and monitors the PWM signal from the linked channels. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect.
Timer Interface Module (TIM) 11.7.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 11.7.2 Stop Mode The TIM is inactive after the execution of a STOP instruction.
Timer Interface Module (TIM) I/O Signals 11.9 I/O Signals Port B shares four of its pins with the TIM channel I/O pins: T1CH0, T1CH1, T2CH0, and T2CH1. Port D shares two of its pins with the TIM clock input pins: T1CLK and T2CLK 11.9.1 TIM Clock Pins (PTD4/KBI4/T1CLK, PTD5/KBI5/T2CLK) T[1,2]CLK is an external clock input that can be the clock source for the TIM[1,2] counter instead of the prescaled internal bus clock.
Timer Interface Module (TIM) 11.10 I/O Registers NOTE: References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC AND T2SC.
Timer Interface Module (TIM) I/O Registers TOF — TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF.
Timer Interface Module (TIM) PS[2:0] — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 11-2 shows. Reset clears the PS[2:0] bits. Table 11-2.
Timer Interface Module (TIM) I/O Registers Address: T1CNTL, $0022 and T2CNTL, $002D Read: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 11-6. TIM Counter Registers Low (TCNTL) 11.10.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter.
Timer Interface Module (TIM) 11.10.
Timer Interface Module (TIM) I/O Registers CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x status and control register with CHxF set and then writing a logic 0 to CHxF.
Timer Interface Module (TIM) When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See Table 11-3. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC).
Timer Interface Module (TIM) I/O Registers NOTE: Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. User software should also clear CHxF before setting CHxIE to avoid any false interrupts. TOVx — Toggle On Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect.
Timer Interface Module (TIM) In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Data Sheet — MC68HC908LJ24 Section 12. Real Time Clock (RTC) 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12.4 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 12.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 12.5.1 Time Functions. . . . . . . .
Real Time Clock (RTC) 12.10.10 12.10.11 12.10.12 12.10.13 12.10.14 Day Register (DAYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Month Register (MTHR) . . . . . . . . . . . . . . . . . . . . . . . . . . .243 Year Register (YRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Day-Of-Week Register (DOWR) . . . . . . . . . . . . . . . . . . . . 244 Chronograph Data Register (CHRR) . . . . . . . . . . . . . . . . . 244 12.
Real Time Clock (RTC) I/O Pins 12.4 I/O Pins Two RTC clock calibration pins are shared with standard port I/O pins. Table 12-1. Pin Name Conventions RTC Generic Pin Name Full MCU Pin Name Pin Selected for RTC Function by Bits in RTCCOMR ($0040) CALIN PTD0/SS/CALIN AUTOCAL CALOUT PTD3/SPSCK/CALOUT (1) OUTF[1:0} Notes: 1. Do not enable the SPI function if the pin is used for RTC calibration. Addr.
Real Time Clock (RTC) $0046 $0047 $0048 $0049 $004A $004B 0 0 0 0 0 Read: Second Register Write: (SECR) Reset: 0 0 0 0 Read: Minute Register Write: (MINR) Reset: 0 0 0 Read: Hour Register Write: (HRR) Reset: AH4 AH3 AH2 AH1 AH0 0 U U U U U SEC5 SEC4 SEC3 SEC2 SEC1 SEC0 U U U U U U MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 0 U U U U U U 0 0 0 HR4 HR3 HR2 HR1 HR0 0 0 0 U U U U U Read: Day Register Write: (DAYR) Reset: 0 0 0 DAY4 DAY3 DAY2 DA
Real Time Clock (RTC) Functional Description 12.5 Functional Description The RTC module provides clock indications in seconds, minutes, and hours; calendar indications in day-of-week, day-of-month, month, and year; with automatic adjustment for month and leap year. Reading the clock and calendar registers return the current time and date. Writing to these registers set the time and date, and the counters will continue to count from the new settings. The alarm interrupt is set for the hour and minute.
Real Time Clock (RTC) CALOUT CALIN 1Hz CLOCK CALIBRATION AND REFERENCE 1Hz COMPENSATION CIRCUIT TBH = 0 => X,Y = A TBH = 1 => X,Y = B TBH TO CLOCK COUNTERS SL CGMXCLK (32.
Real Time Clock (RTC) Functional Description 12.5.1 Time Functions Real time clock functions are provided by the second, minute, and hour counter registers. All three clock counters are able to generate interrupts on every counter increment, providing periodic interrupts for the second (SECF), minute (MINF), and hour (HRF). A CPU interrupt request is generated if the corresponding enable bit (SECIE, MINIE, and HRIE) is also set. 12.5.
Real Time Clock (RTC) The value in the chronograph data register satisfies the following equation: (128Hz counter value × 25) + 16------------------------------------------------------------------------------------32 The accuracy of the chronograph counter is ±5ms (max). 12.5.5 Timebase Interrupts In addition to the second, minute, hour, and day periodic interrupts generated by the clock functions, the divider circuits generates four periodic clocks, separated into two groups: 2Hz and 4Hz; 8Hz and 16Hz.
Real Time Clock (RTC) RTC Clock Calibration and Compensation 12.7 RTC Clock Calibration and Compensation The RTC module is built with a calibration and compensation circuit for the CGMXCLK. The circuit is used to compensate frequency errors of the 32.768kHz crystal so that a more accurate 1-Hz RTC clock can be achieved. Using this method, it is possible to use a less expensive crystal.
Real Time Clock (RTC) A negative E-value indicates the number of CGMXCLK cycles that needs to be subtracted, because the CGMXCLK is slower than the ideal 32.768kHz; 32768 CGMXCLK cycles will be more longer than 1-second. A positive E-value indicates the number of CGMXCLK cycles that needs to be added, because the CGMXCLK is faster than the ideal 32.768kHz; 32768 CGMXCLK cycles will be more shorter than 1-second.
Real Time Clock (RTC) RTC Register and Bit Write Protection TRUE 15 SECONDS CGMXCLK UNCOMPENSATED 1-Hz CLOCK (CGMXCLK ÷ 32768) COMPENSATED 1-Hz CLOCK PERIOD A PERIOD B 1-Hz CLOCK = CGMXCLK ÷ A 1-Hz CLOCK = CGMXCLK ÷ B Figure 12-4. 1-Hz Clock Compensation 12.8 RTC Register and Bit Write Protection A write-protect mechanism is implemented to prevent accidental writes to the RTC clock registers, calendar registers, and other control bits. The protected RTC registers and bits are listed in Table 12-3.
Real Time Clock (RTC) The mechanism uses the RTCWE[1:0] bits in the RTC calibration control register (RTCCOMR) in a state machine, which requires a bit-write sequence to disable the write-protection. A block diagram of the state machine is shown in Figure 12-5. R ESET Write-Protect ENABLED Write-Protect DISABLED Write 10 W to RTCW E rite 10 Write any value other than 10 to RTWE to E CW RT Write RTCWE = 10 CWE 0 to RT Write 11 to Note: Reading RTCWE[1:0] always return 00.
Real Time Clock (RTC) Low-Power Modes RTCWE_R EQU $40 ... RTC_WRTIE_PROTECT ;RTCCOMR register BSET BSET RTCWE1,RTCWE_R ;write %10 RTCWE1,RTCWE_R ;write %10 again ... To disable write-protect after write-protect is enabled execute the following code: RTCWE1 EQU 1 RTCWE0 EQU 0 RTCWE_R EQU $40 ...
Real Time Clock (RTC) 12.9.2 Stop Mode For continuous RTC operation in stop mode, the oscillator stop mode enable bit (STOP_XCLKEN in CONFIG2 register) must be set before executing the STOP instruction. When STOP_XCLKEN is set, CGMXCLK continues to drive the RTC module, and any enabled CPU interrupt request from the RTC can bring the MCU out of stop mode. If STOP_XCLKEN bit is cleared, the RTC module is inactive after the execution of a STOP instruction.
Real Time Clock (RTC) RTC Registers 12.10.1 RTC Calibration Control Register (RTCCOMR) The RTC calibration control register (RTCCOMR) contains control bits for RTC calibration, output option for the CALOUT pin, and registers/bits write-protect enable. Address: $0040 Read: 0 0 Write: R R Reset: 0 0 CAL* AUTOCAL* OUTF1* OUTF0* 0 0 0 0 0 0 RTCWE1 RTCWE0 0 0 * CAL, AUTOCAL, and OUTF{1:0] bits are write-protected; unprotect by a write sequence to RTCWE[1:0]. Figure 12-6.
Real Time Clock (RTC) OUTF[1:0] — Calibration Mode CALOUT Pin Output Selection These two bits select the output option for the CALOUT pin. When CAL = 0, OUTF[1:0] is always 00. Table 12-4. CALOUT Pin Output Option OUTF[1:0] CALOUT Pin Output 00 CALOUT pin is disconnected. 01 CALOUT pin outputs compensated 1-Hz. 10 CALOUT pin outputs CGMXCLK clock. 11 Reserved RTCWE[1:0] — RTC Module Write Enable These two write-only bits control the write-protect function of several RTC registers and bits.
Real Time Clock (RTC) RTC Registers 12.10.2 RTC Calibration Data Register (RTCCDAT) The RTC calibration data register (RTCCDAT) contains the RTC calibration data. Address: $0041 Read: EOVL 0 U 0 Write: Reset: E5 E4 E3 E2 E1 E0 U U U U U U Figure 12-7.
Real Time Clock (RTC) 12.10.3 RTC Control Register 1 (RTCCR1) The RTC control register 1 (RTCCR1) contains the eight interrupt enable bits for RTC interrupt functions. Address: Read: Write: Reset: $0042 ALMIE CHRIE DAYIE HRIE MINIE SECIE TB1IE TB2IE 0 0 0 0 0 0 0 0 Figure 12-8. RTC Control Register 1 (RTCCR1) ALMIE — Alarm Interrupt Enable This read/write bit enables the alarm flag, ALMF, to generate CPU interrupt requests. Reset clears the ALMIE bit.
Real Time Clock (RTC) RTC Registers SECIE — Second Interrupt Enable This read/write bit enables the second flag, SECF, to generate CPU interrupt requests. Reset clears the SECIE bit. 1 = SECF enabled to generate CPU interrupt 0 = SECF not enabled to generate CPU interrupt TB1IE — Timebase 1 Interrupt Enable This read/write bit enables the timebase1 flag, TB1F, to generate CPU interrupt requests. Reset clears the TB1IE bit.
Real Time Clock (RTC) NOTE: With compensation enabled, the RTC clock and calendar register updates may not be synchronized to the timebase and chronograph clocks, since their clocks are derived from the uncompensated CGMXCLK. Hence, time intervals for timebase ticks may not align with the RTC clock and calendar register updates. CHRCLR — Chronograph counter clear Setting this write-only bit resets the chronograph counter and the chronograph data register (CHRR).
Real Time Clock (RTC) RTC Registers 12.10.5 RTC Status Register (RTCSR) The RTC status register contains eight status flags. When a flag is set and the corresponding interrupt enable bit is also set, a CPU interrupt request is generated. Address: $0044 Read: ALMF CHRF DAYF HRF MINF SECF TB1F TB2F 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 12-10.
Real Time Clock (RTC) DAYF — Day Flag This clearable, read-only bit is set on every increment of the day counter. When the DAYIE bit in RTCCR1 is set, DAYF generates a CPU interrupt request. In normal operation, clear the DAYF bit by reading RTCSR with DAYF set and then reading the day register (DAYR). Reset clears DAYF. 1 = Day counter incremented 0 = No day counter incremented HRF — Hour Flag This clearable, read-only bit is set on every increment of the hour counter.
Real Time Clock (RTC) RTC Registers TB1F — Timebase 1 Flag This clearable, read-only bit is set on every tick of the timebase 1 counter (every 0.5 or 0.125 seconds). When the TB1IE bit in RTCCR1 is set, TB1F generates a CPU interrupt request. In normal operation, clear the TB1F bit by reading RTCSR with TB1F set and then reading the chronograph data register (CHRR). Reset clears TB1F.
Real Time Clock (RTC) 12.10.6 Alarm Minute and Hour Registers (ALMR and ALHR) These read/write registers contain the alarm minute and hour values for the hour and minute alarm function. When the hour counter matches the value in the alarm hour register (ALHR) and the minute counter matches the value in the alarm minute register (ALMR), the alarm flag, ALMF, is set. When ALMF is set and the alarm interrupt enable bit, ALMIE, is also set, a CPU interrupt request is generated.
Real Time Clock (RTC) RTC Registers 12.10.7 Second Register (SECR) This read/write register contains the current value of the second counter. This register can be read at any time without affecting the counter count. Writing to this register loads the value to the second counter and the counter continues to count from this new value. The second counter rolls over to 0 ($00) after reaching 59 ($4B). Writing a value other than 0 to 59 to this register has no effect.
Real Time Clock (RTC) 12.10.9 Hour Register (HRR) This read/write register contains the current value of the hour counter. This register can be read at any time without affecting the counter count. Writing to this register loads the value to the hour counter and the counter continues to count from this new value. The hour counter rolls over to 0 ($00) after reaching 23 ($17). Writing a value other than 0 to 23 to this register has no effect.
Real Time Clock (RTC) RTC Registers 12.10.11 Month Register (MTHR) This read/write register contains the current value of the month counter. This register can be read at any time without affecting the counter count. Writing to this register loads the value to the month counter and the counter continues to count from this new value. The month counter rolls over to 1 ($01) after reaching 12 ($0B). Writing a value other than 1 to 12 to this register has no effect.
Real Time Clock (RTC) 12.10.13 Day-Of-Week Register (DOWR) This read/write register contains the current value of the day-of-week counter. This register can be read at any time without affecting the counter count. Writing to this register loads the value to the day-of-week counter and the counter continues to count from this new value. The day-of-week counter value rolls over to 0 ($00) after reaching 6 ($06). Writing a value other than 0 to 6 to this register has no effect.
Data Sheet — MC68HC908LJ24 Section 13. Infrared Serial Communications Interface Module (IRSCI) 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 13.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.5 IRSCI Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.
Infrared Serial Communications 13.9 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .267 13.10 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.10.1 PTB0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . 267 13.10.2 PTB1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.11 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 13.11.
Infrared Serial Communications Interface Module (IRSCI) Features 13.
Infrared Serial Communications Addr.
Infrared Serial Communications Interface Module (IRSCI) Pin Name Conventions 13.4 Pin Name Conventions The generic names of the IRSCI I/O pins are: • RxD (receive data) • TxD (transmit data) IRSCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full name of an IRSCI input or output reflects the name of the shared port pin. Table 13-1 shows the full names and the generic names of the IRSCI I/O pins. The generic pin names appear in the text of this section. Table 13-1.
Infrared Serial Communications The infrared sub-module receives two clock sources from the SCI module: SCI_R16XCLK and SCI_R32XCLK. Both reference clocks are used to generate the narrow pulses during data transmission. The SCI_R16XCLK and SCI_R32XCLK are internal clocks with frequencies that are 16 and 32 times the baud rate respectively. Both SCI_R16XCLK and SCI_R32XCLK clocks are used for transmitting data. The SCI_R16XCLK clock is used only for receiving data.
Infrared Serial Communications Interface Module (IRSCI) Infrared Functional Description The sub-module consists of two main blocks: the transmit encoder and the receive decoder. When transmitting data, the SCI data stream is encoded by the infrared sub-module. For every "0" bit, a narrow "low" pulse is transmitted; no pulse is transmitted for "1" bits.
Infrared Serial Communications 13.7 SCI Functional Description Figure 13-5 shows the structure of the SCI.
Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data.
Infrared Serial Communications 13.7.2 Transmitter Figure 13-7 shows the structure of the SCI transmitter. The baud rate clock source for the SCI can be selected by the CKS bit, in the SCI baud rate register (see 13.11.7 SCI Baud Rate Register).
Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description 13.7.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). 13.7.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the TxD pin.
Infrared Serial Communications 13.7.2.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register.
Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description NOTE: When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin. Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost. Toggle the TE bit for a queued idle character when the SCTE bit becomes set and just before writing the next byte to the SCDR. 13.7.2.
Infrared Serial Communications INTERNAL BUS SCR1 SCR0 PRESCALER SL = 0 => X = A SL = 1 => X = B BAUD DIVIDER ÷ 16 DATA RECOVERY SCI_RxD BKF CPU INTERRUPT REQUEST 11-BIT RECEIVE SHIFT REGISTER H 8 7 6 5 M WAKE ILTY PEN PTY 4 3 2 1 0 L ALL 0s RPF ERROR CPU INTERRUPT REQUEST DMA SERVICE REQUEST SCI DATA REGISTER START SCP0 STOP A SL X B SCR2 ALL 1s CGMXCLK BUS CLOCK SCP1 MSB CKS SCRF WAKEUP LOGIC RWU IDLE R8 PARITY CHECKING IDLE ILIE DMARE ILIE SCRF SCRIE DMARE SCRIE SCR
Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description 13.7.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR.
Infrared Serial Communications To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 13-2 summarizes the results of the start bit verification samples. Table 13-2.
Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-4 summarizes the results of the stop bit samples.
Infrared Serial Communications As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. Slow Data Tolerance Figure 13-10 shows how much a slow received character can be misaligned without causing a noise error or a framing error.
Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 170 – 163 × 100 = 4.12% -------------------------170 Fast Data Tolerance Figure 13-11 shows how much a fast received character can be misaligned without causing a noise error or a framing error.
Infrared Serial Communications The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 170 – 176 × 100 = 3.53% -------------------------170 13.7.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state.
Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description 13.7.3.7 Receiver Interrupts The following sources can generate CPU interrupt requests from the SCI receiver: • SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR. SCRF can generate a receiver interrupt request. Setting the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU interrupts.
Infrared Serial Communications 13.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 13.8.1 Wait Mode The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode.
Infrared Serial Communications Interface Module (IRSCI) SCI During Break Module Interrupts 13.9 SCI During Break Module Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during interrupts generated by the break module. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit.
Infrared Serial Communications Table 13-5 shows a summary of I/O pin functions when the SCI is enabled. Table 13-5.
Infrared Serial Communications Interface Module (IRSCI) I/O Registers 13.11.1 SCI Control Register 1 SCI control register 1: • Enables loop mode operation • Enables the SCI • Controls output polarity • Controls character length • Controls SCI wakeup method • Controls idle character detection • Enables parity function • Controls parity type Address: Read: Write: Reset: $0013 Bit 7 6 LOOPS ENSCI 0 0 5 0 0 4 3 2 1 Bit 0 M WAKE ILTY PEN PTY 0 0 0 0 0 Figure 13-12.
Infrared Serial Communications M — Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 13-6.) The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M bit.
Infrared Serial Communications Interface Module (IRSCI) I/O Registers PTY — Parity Bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity. (See Table 13-6.) Reset clears the PTY bit. 1 = Odd parity 0 = Even parity NOTE: Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Table 13-6.
Infrared Serial Communications Address: Read: Write: Reset: $0014 Bit 7 6 5 4 3 2 1 Bit 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 13-13. SCI Control Register 2 (SCC2) SCTIE — SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset clears the SCTIE bit.
Infrared Serial Communications Interface Module (IRSCI) I/O Registers (logic 1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit. 1 = Transmitter enabled 0 = Transmitter disabled NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RE — Receiver Enable Bit Setting this read/write bit enables the receiver.
Infrared Serial Communications 13.11.3 SCI Control Register 3 SCI control register 3: • Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted • Enables the following interrupts: – Receiver overrun interrupts – Noise error interrupts – Framing error interrupts – Parity error interrupts Address: $0015 Bit 7 Read: R8 Write: Reset: U 6 5 4 3 2 1 Bit 0 T8 DMARE DMATE ORIE NEIE FEIE PEIE U 0 0 0 0 0 0 = Unimplemented U = Unaffected Figure 13-14.
Infrared Serial Communications Interface Module (IRSCI) I/O Registers DMARE — DMA Receive Enable Bit CAUTION: The DMA module is not included on this MCU. Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance.
Infrared Serial Communications PEIE — Receiver Parity Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the parity error bit, PE. (See 13.11.4 SCI Status Register 1.) Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled 13.11.
Infrared Serial Communications Interface Module (IRSCI) I/O Registers operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register TC — Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted.
Infrared Serial Communications OR — Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit.
Infrared Serial Communications Interface Module (IRSCI) I/O Registers BYTE 1 BYTE 2 BYTE 3 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 NORMAL FLAG CLEARING SEQUENCE BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1 READ SCDR BYTE 2 READ SCDR BYTE 3 BYTE 1 BYTE 2 BYTE 3 SCRF = 0 OR = 0 SCRF = 1 OR = 1 SCRF = 0 OR = 1 SCRF = 1 SCRF = 1 OR = 1 DELAYED FLAG CLEARING SEQUENCE BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF
Infrared Serial Communications 13.11.5 SCI Status Register 2 (SCS2) SCI status register 2 contains flags to signal the following conditions: • Break character detected • Incoming data Address: Read: $0017 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 BKF RPF 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 13-17. SCI Status Register 2 (SCS2) BKF — Break Flag Bit This clearable, read-only bit is set when the SCI detects a break character on the RxD pin.
Infrared Serial Communications Interface Module (IRSCI) I/O Registers 13.11.6 SCI Data Register The SCI data register is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register. Address: $0018 Bit 7 6 5 4 3 2 1 Bit 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by reset Figure 13-18.
Infrared Serial Communications 13.11.7 SCI Baud Rate Register The baud rate register selects the baud rate for both the receiver and the transmitter. Address: $0019 Bit 7 Read: Write: Reset: CKS 0 6 0 5 4 3 2 1 Bit 0 SCP1 SCP0 R SCR2 SCR1 SCR0 0 0 0 0 0 0 R = Reserved 0 = Unimplemented Figure 13-19. SCI Baud Rate Register (SCBR) CKS — Baud Clock Input Select This read/write bit selects the source clock for the baud rate generator. Reset clears the CKS bit, selecting CGMXCLK.
Infrared Serial Communications Interface Module (IRSCI) I/O Registers Table 13-8.
Infrared Serial Communications Table 13-9. SCI Baud Rate Selection Examples SCP1 and SCP0 Prescaler Divisor (PD) SCR2, SCR1, and SCR0 Baud Rate Divisor (BD) Baud Rate (fBUS = 4.
Infrared Serial Communications Interface Module (IRSCI) I/O Registers 13.11.8 SCI Infrared Control Register The infrared control register contains the control bits for the infrared submodule. • Enables the infrared sub-module • Selects the infrared transmitter narrow pulse width Address: $001A Bit 7 Read: Write: Reset: R 0 6 5 4 0 0 0 0 0 0 = Unimplemented 3 2 1 Bit 0 R TNP1 TNP0 IREN 0 0 0 0 R = Reserved Figure 13-20.
Infrared Serial Communications Data Sheet 286 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 14. Serial Peripheral Interface Module (SPI) 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.4 Pin Name Conventions and I/O Register Addresses . . . . . . . 289 14.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 14.5.1 Master Mode . . . . . . . . . . . . . . .
Serial Peripheral Interface Module (SPI) 14.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 14.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 14.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 14.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 14.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 14.14.
Serial Peripheral Interface Module (SPI) Pin Name Conventions and I/O Register Addresses 14.4 Pin Name Conventions and I/O Register Addresses The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial clock), CGND (clock ground), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel I/O ports. The full names of the SPI I/O pins are shown in Table 14-1. The generic pin names appear in the text that follows.
Serial Peripheral Interface Module (SPI) 14.5 Functional Description Figure 14-2 shows the structure of the SPI module.
Serial Peripheral Interface Module (SPI) Functional Description 14.5.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set. NOTE: Configure the SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. (See 14.14.1 SPI Control Register.) Only a master SPI module can initiate transmissions.
Serial Peripheral Interface Module (SPI) The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. (See 14.14.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set.
Serial Peripheral Interface Module (SPI) Transmission Formats When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. Otherwise, the byte already in the slave shift register shifts out on the MISO pin.
Serial Peripheral Interface Module (SPI) The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.
Serial Peripheral Interface Module (SPI) Transmission Formats SPSCK CYCLE # FOR REFERENCE 1 2 3 4 5 6 7 8 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE MSB SS; TO SLAVE CAPTURE STROBE Figure 14-4. Transmission Format (CPHA = 0) MISO/MOSI BYTE 1 BYTE 2 BYTE 3 MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 Figure 14-5.
Serial Peripheral Interface Module (SPI) 14.6.3 Transmission Format When CPHA = 1 Figure 14-6 shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1.
Serial Peripheral Interface Module (SPI) Transmission Formats When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of SPSCK.
Serial Peripheral Interface Module (SPI) WRITE TO SPDR INITIATION DELAY BUS CLOCK MOSI MSB BIT 6 1 2 BIT 5 SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER 3 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN WRITE TO SPDR BUS CLOCK EARLIEST LATEST WRITE TO SPDR SPSCK = INTERNAL CLOCK ÷ 2; 2 POSSIBLE START POINTS BUS CLOCK EARLIEST WRITE TO SPDR SPSCK = INTERNAL CLOCK ÷ 8; 8 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK ÷ 32; 32 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK ÷
Serial Peripheral Interface Module (SPI) Queuing Transmission Data 14.7 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when the SPTE bit is high.
Serial Peripheral Interface Module (SPI) For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible.
Serial Peripheral Interface Module (SPI) Error Conditions interrupts share the same CPU interrupt vector. (See Figure 14-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 14-9 shows how it is possible to miss an overflow.
Serial Peripheral Interface Module (SPI) BYTE 1 SPI RECEIVE COMPLETE BYTE 2 5 1 BYTE 3 7 BYTE 4 11 SPRF OVRF READ SPSCR 2 READ SPDR 4 6 3 1 BYTE 1 SETS SPRF BIT. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. 3 9 8 12 10 14 13 8 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. 9 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 4 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 11 BYTE 4 SETS SPRF BIT.
Serial Peripheral Interface Module (SPI) Error Conditions MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 14-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set.
Serial Peripheral Interface Module (SPI) slave. This happens because SS at logic 0 indicates the start of the transmission (MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun. In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set.
Serial Peripheral Interface Module (SPI) Interrupts Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register. The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests, provided that the SPI is enabled (SPE = 1).
Serial Peripheral Interface Module (SPI) The following sources in the SPI status and control register can generate CPU interrupt requests: • SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF generates an SPI receiver/error CPU interrupt request.
Serial Peripheral Interface Module (SPI) Low-Power Modes By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set. 14.11 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 14.11.
Serial Peripheral Interface Module (SPI) 14.12 SPI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See Section 9. System Integration Module (SIM).) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit.
Serial Peripheral Interface Module (SPI) I/O Signals The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD. 14.13.
Serial Peripheral Interface Module (SPI) 14.13.3 SPSCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port. 14.13.
Serial Peripheral Interface Module (SPI) I/O Signals When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. (See 14.8.2 Mode Fault Error.) For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data direction register of the shared I/O port.
Serial Peripheral Interface Module (SPI) 14.14 I/O Registers Three registers control and monitor SPI operation: • SPI control register (SPCR) • SPI status and control register (SPSCR) • SPI data register (SPDR) 14.14.
Serial Peripheral Interface Module (SPI) I/O Registers SPMSTR — SPI Master Bit This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit. 1 = Master mode 0 = Slave mode CPOL — Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure 14-4 and Figure 14-6.) To transmit data between SPI modules, the SPI modules must have identical CPOL values. Reset clears the CPOL bit.
Serial Peripheral Interface Module (SPI) 14.14.
Serial Peripheral Interface Module (SPI) I/O Registers ERRIE — Error Interrupt Enable Bit This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests OVRF — Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register.
Serial Peripheral Interface Module (SPI) MODFEN — Mode Fault Enable Bit This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low, then the SS pin is available as a general-purpose I/O. If the MODFEN bit is set, then this pin is not available as a generalpurpose I/O.
Serial Peripheral Interface Module (SPI) I/O Registers 14.14.3 SPI Data Register The SPI data register consists of the read-only receive data register and the write-only transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate registers that can contain different values. (See Figure 14-2.
Serial Peripheral Interface Module (SPI) Data Sheet 318 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 15. Multi-Master IIC Interface (MMIIC) 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 15.4 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 15.5 Multi-Master IIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 15.5.
Multi-Master IIC Interface (MMIIC) This Multi-master IIC module uses the SCL clock line and the SDA data line to communicate with external DDC host or IIC interface. These two pins are shared with port pins PTD6/KBI6 and PTD7/KBI7 respectively. The outputs of SCL and SDA pins are open-drain type — no clamping diode is connected between the pin and internal VDD. The maximum data rate typically is 750k-bps.
Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers Addr.
Multi-Master IIC Interface (MMIIC) MMAD[7:1] — Multi-Master Address These seven bits represent the MMIIC interface’s own specific slave address when in slave mode, and the calling address when in master mode. Software must update MMAD[7:1] as the calling address while entering master mode and restore its own slave address after master mode is relinquished. This register is cleared as $A0 upon reset. MMEXTAD — Multi-Master Expanded Address This bit is set to expand the address of the MMIIC in slave mode.
Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers 15.5.2 Multi-Master IIC Control Register (MMCR) Address: $006C Read: Write: Reset: Bit 7 6 MMEN MMIEN 0 0 5 4 0 0 0 0 3 2 MMTXAK REPSEN 0 0 1 Bit 0 0 0 0 0 = Unimplemented Figure 15-3. Multi-Master IIC Control Register (MMCR) MMEN — Multi-Master IIC Enable This bit is set to enable the Multi-master IIC module. When MMEN = 0, module is disabled and all flags will restore to its poweron default states.
Multi-Master IIC Interface (MMIIC) REPSEN — Repeated Start Enable This bit is set to enable repeated START signal to be generated when in master mode transfer (MMAST = 1). The REPSEN bit is cleared by hardware after the completion of repeated START signal or when the MMAST bit is cleared. Reset clears this bit. 1 = Repeated START signal will be generated if MMAST bit is set 0 = No repeated START signal will be generated 15.5.
Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers MMBB — Bus Busy Flag This flag is set after a start condition is detected (bus busy), and is cleared when a stop condition (bus idle) is detected. Reset clears this bit. 1 = Start condition detected 0 = Stop condition detected or MMIIC is disabled MMAST — Master Control Bit This bit is set to initiate a master mode transfer.
Multi-Master IIC Interface (MMIIC) Table 15-2. Baud Rate Select MMBR2 MMBR1 MMBR0 Baud Rate 0 0 0 Internal bus clock ÷ 8 0 0 1 Internal bus clock ÷ 16 0 1 0 Internal bus clock ÷ 32 0 1 1 Internal bus clock ÷ 64 1 0 0 Internal bus clock ÷ 128 1 0 1 Internal bus clock ÷ 256 1 1 0 Internal bus clock ÷ 512 1 1 1 Internal bus clock ÷ 1024 15.5.
Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers MMTXIF — Multi-Master Transmit Interrupt Flag This flag is set when data in the data transmit register (MMDTR) is downloaded to the output circuit, and that new data can be written to the MMDTR. MMTXIF generates an interrupt request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or when the MMEN = 0.
Multi-Master IIC Interface (MMIIC) MMTXBE — Multi-Master Transmit Buffer Empty This flag indicates the status of the data transmit register (MMDTR). When the CPU writes the data to the MMDTR, the MMTXBE flag will be cleared. MMTXBE is set when MMDTR is emptied by a transfer of its data to the output circuit. Reset sets this bit. 1 = Data transmit register empty 0 = Data transmit register full MMRXBF — Multi-Master Receive Buffer Full This flag indicates the status of the data receive register (MMDRR).
Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers If the calling master does not return an acknowledge bit (MMRXAK = 1), the module will release the SDA line for master to generate a "stop" or "repeated start" condition. The data in the MMDTR will not be transferred to the output circuit until the next calling from a master. The transmit buffer empty flag remains cleared (MMTXBE = 0).
Multi-Master IIC Interface (MMIIC) In slave mode, the data in MMDRR is: • the calling address from the master when the address match flag is set (MMATCH = 1); or • the last data received when MMATCH = 0. In master mode, the data in the MMDRR is: • the last data received. When the MMDRR is read by the CPU, the receive buffer full flag is cleared (MMRXBF = 0), and the next received data is loaded to the MMDRR.
Multi-Master IIC Interface (MMIIC) Programming Considerations (a) Master Transmit Mode START Address MMTXBE=0 MMRW=0 MMAST=1 Data1 → MMDTR 0 ACK TX Data1 ACK MMTXBE=1 MMTXIF=1 Data3 → MMDTR MMTXBE=1 MMTXIF=1 Data2 → MMDTR TX DataN ACK STOP MMTXBE=1 MMNAKIF=1 MMTXIF=1 MMAST=0 DataN+2 → MMDTR MMTXBE=0 (b) Master Receive Mode START Address 1 ACK RX Data1 ACK Data1 → MMDRR MMRXIF=1 MMRXBF=1 MMRXBF=0 MMRW=1 MMAST=1 MMTXBE=0 (dummy data → MMDTR) RX DataN NAK STOP DataN → MMDRR MMNAKIF=1 M
Multi-Master IIC Interface (MMIIC) Data Sheet 332 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 16. Analog-to-Digital Converter (ADC) 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 16.4 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.2 Voltage Conversion . . . . . .
Analog-to-Digital Converter (ADC) 16.2 Introduction This section describes the analog-to-digital convert (ADC). The ADC is a 6-channel 10-bit linear successive approximation ADC. 16.
Analog-to-Digital Converter (ADC) Functional Descriptions Addr.
Analog-to-Digital Converter (ADC) logic and can be used as general-purpose I/O pins. Writes to the port data register or data direction register will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return the pin condition if the corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read.
Analog-to-Digital Converter (ADC) Functional Descriptions 16.4.2 Voltage Conversion When the input voltage to the ADC equals VREFH, the ADC converts the signal to $3FF (full scale). If the input voltage equals VREFL, the ADC converts it to $000. Input voltages between VREFH and VREFL are straight-line linear conversions. All other input voltages will result in $3FF if greater than VREFH and $000 if less than VREFL. NOTE: Input voltage should not exceed the analog supply voltages. 16.4.
Analog-to-Digital Converter (ADC) 16.4.4 Continuous Conversion In the continuous conversion mode, the ADC continuously converts the selected channel, filling the ADC data register (ADRH:ADRL) with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared.
Analog-to-Digital Converter (ADC) Functional Descriptions Finally, 8-bit truncation mode will place the eight MSBs in ADC data register low (ADRL). The two LSBs are dropped. This mode of operation is used when compatibility with 8-bit ADC designs are required. No interlocking between ADRH and ADRL is present. NOTE: Quantization error is affected when only the most significant eight bits are used as a result. See Figure 16-3.
Analog-to-Digital Converter (ADC) 16.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled. The interrupt vector is defined in Table 2-1 . Vector Addresses. 16.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low powerconsumption standby modes. 16.6.
Analog-to-Digital Converter (ADC) I/O Signals 16.7.1 ADC Voltage In (VADIN) VADIN is the input voltage signal from one of the ten channels to the ADC module. 16.7.2 ADC Analog Power Pin (VDDA) The ADC analog portion uses VDDA as its power pin. Connect the VDDA pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDA for good results. NOTE: Route VDDA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 16.7.
Analog-to-Digital Converter (ADC) 16.8 I/O Registers These I/O registers control and monitor operation of the ADC: • ADC status and control register, (ADSCR) • ADC data register (ADRH:ADRL) • ADC clock control register (ADCLK) 16.8.1 ADC Status and Control Register This section describes the function of the ADC status and control register (ADSCR). Writing ADSCR aborts the current conversion and initiates a new conversion.
Analog-to-Digital Converter (ADC) I/O Registers ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADC data register at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion ADCH[4:0] — ADC Channel Select Bits ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels when not in auto-scan mode.
Analog-to-Digital Converter (ADC) 16.8.2 ADC Data Register The ADC data register consist of a pair of 8-bit registers: high byte (ADRH), and low byte (ADRL). This pair form a 16-bit register to store the 10-bit ADC result for the selected ADC result justification mode. In 8-bit truncated mode, the ADRL holds the eight most significant bits (MSBs) of the 10-bit result. The ADRL is updated each time an ADC conversion completes. In 8-bit truncated mode, ADRL contains no interlocking with ADRH.
Analog-to-Digital Converter (ADC) I/O Registers In left justified mode the ADRH holds the eight most significant bits (MSBs), and the ADRL holds the two least significant bits (LSBs), of the 10-bit result. The ADRH and ADRL are updated each time a single channel ADC conversion completes. Reading ADRH latches the contents of ADRL. Until ADRL is read all subsequent ADC results will be lost. (See Figure 16-7 . ADRH and ADRL in Left Justified Mode.) Addr.
Analog-to-Digital Converter (ADC) 16.8.3 ADC Clock Control Register The ADC clock control register (ADCLK) selects the clock frequency for the ADC. Address: Read: Write: Reset: $003F ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 0 0 0 0 0 1 = Unimplemented R 0 0 R 0 0 = Reserved Figure 16-9. ADC Clock Control Register (ADCLK) ADIV[2:0] — ADC Clock Prescaler Bits ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock.
Analog-to-Digital Converter (ADC) I/O Registers If the external clock (CGMXCLK) is equal to or greater than 1MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at fADIC, correct operation can be guaranteed.
Analog-to-Digital Converter (ADC) Data Sheet 348 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 17. Liquid Crystal Display (LCD) Driver 17.1 Contents 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 17.4 Pin Name Conventions and I/O Register Addresses . . . . . . . 350 17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 17.5.1 LCD Duty . . . . . . . . . . . . . . . . . . .
Liquid Crystal Display (LCD) Driver 17.2 Introduction This section describes the liquid crystal display (LCD) driver module. The LCD driver module can drive a maximum of 33 frontplanes and 4 backplanes, depending on the LCD duty selected. 17.
Liquid Crystal Display (LCD) Driver Pin Name Conventions and I/O Register Addresses Addr.
Liquid Crystal Display (LCD) Driver Read: LCD Data Register 9 Write: (LDAT9) Reset: $005A $005B $005C $005D $005E $005F $0060 $0061 $0062 Read: LCD Data Register 10 Write: (LDAT10) Reset: Read: LCD Data Register 11 Write: (LDAT11) Reset: Read: LCD Data Register 12 Write: (LDAT12) Reset: Read: LCD Data Register 13 Write: (LDAT13) Reset: Read: LCD Data Register 14 Write: (LDAT14) Reset: Read: LCD Data Register 15 Write: (LDAT15) Reset: Read: LCD Data Register 16 Write: (LDAT16) Reset: F17B3 F17B2
Liquid Crystal Display (LCD) Driver Functional Description 17.5 Functional Description Figure 17-2 shows a block diagram of the LCD driver module, and Figure 17-3 shows a simplified schematic of the LCD system. The LCD driver module uses a 1/3 biasing method. The LCD power is supplied by the VLCD pin. Voltages VLCD1, VLCD2, and VLCD3 are generated by an internal resistor ladder. The LCD data registers, LDAT1–LDAT17, control the LCD segments’ ON/OFF, with each data register controlling two frontplanes.
Liquid Crystal Display (LCD) Driver LCD FP0 FP1 RFP RFP FP24 RFP BP0 RBP BP1 BP2 RBP RBP VLCD VLCD RLCD RLCD RLCD VLCD1 VLCD2 VLCD3 Vbias VR BIAS CONTROL LCCON[3:0] Figure 17-3. Simplified LCD Schematic (1/3 Duty, 1/3 Bias) Data Sheet 354 MC68HC908LJ24/LK24 — Rev. 2.
Liquid Crystal Display (LCD) Driver Functional Description 17.5.1 LCD Duty The setting of the LCD output waveform duty is dependent on the number of backplane drivers required. Three LCD duties are available: • Static duty — BP0 is used only • 1/3 duty — BP0, BP1, and BP3 are used • 1/4 duty — BP0, BP1, BP2, and BP3 are used When the LCD driver module is enabled the backplane waveforms for the selected duty are driven out of the backplane pins.
Liquid Crystal Display (LCD) Driver The LCD cycle frame is determined by the equation: LCD CYCLE FRAME = 1 LCD WAVEFORM BASE CLOCK × DUTY For example, for 1/3 duty and 256Hz waveform base clock: LCD CYCLE FRAME = 1 256 × (1/3) = 11.72 ms 17.5.4 Fast Charge and Low Current The default value for each of the bias resistors (see Figure 17-3), RLCD, in the resistor ladder is approximately 37kΩ at VLCD = 3V.
Liquid Crystal Display (LCD) Driver Low-Power Modes LCDCLK LCD WAVEFORM EXAMPLE: BP0 FAST CHARGE CLOCK HIGH CURRENT SELECTED BEFORE SWITCHING EDGE, PERIOD IS DEFINED BY FCCTL[1:0] Figure 17-4. Fast Charge Timing 17.5.5 Contrast Control The contrast of the connected LCD panel can be adjusted by configuring the LCCON[3:0] bits in the LCD control register. The LCCON[3:0] bits provide a 16-step contrast control, which adjusts the bias voltage in the resistor ladder for LCD voltage, VLCD3.
Liquid Crystal Display (LCD) Driver 17.6.1 Wait Mode The LCD driver module continues normal operation in wait mode. If the LCD is not required in wait mode, power down the LCD module by clearing the LCDE bit before executing the WAIT instruction. 17.6.2 Stop Mode For continuous LCD module operation in stop mode, the oscillator stop mode enable bit (STOP_XCLKEN in CONFIG2 register) must be set before executing the STOP instruction. When STOP_XCLKEN is set, CGMXCLK continues to drive the LCD module.
Liquid Crystal Display (LCD) Driver I/O Signals 17.7.1 BP0–BP3 (Backplane Drivers) BP0–BP3 are the backplane driver output pins. These are connected to the backplane of the LCD panel. Depending on the LCD duty selected, the voltage waveforms in Figure 17-5, Figure 17-6, and Figure 17-7 appear on the backplane pins. BP3 pin is only used when 1/4 duty is selected. The pin becomes FP0 for static and 1/3 duty operations. DUTY = STATIC 1FRAME VLCD VLCD1 VLCD2 BP0 VLCD3 NOTES: 1.
Liquid Crystal Display (LCD) Driver DUTY = 1/4 1FRAME VLCD VLCD1 VLCD2 BP0 VLCD3 BP1 VLCD VLCD1 VLCD2 VLCD3 BP2 VLCD VLCD1 VLCD2 VLCD3 BP3 VLCD VLCD1 VLCD2 VLCD3 Figure 17-7. 1/4 Duty LCD Backplane Driver Waveforms Data Sheet 360 MC68HC908LJ24/LK24 — Rev. 2.
Liquid Crystal Display (LCD) Driver I/O Signals 17.7.2 FP0–FP32 (Frontplane Drivers) FP0–FP32 are the frontplane driver output pins. These are connected to the frontplane of the LCD panel. Depending on LCD duty selected and the contents in the LCD data registers, the voltage waveforms in Figure 17-8, Figure 17-9, Figure 17-10 and Figure 17-11 appear on the frontplane pins. FP11–FP18 are shared with port E I/O pins. These pins are configured for standard I/O or LCD use by the PEE bit in CONFIG2 register.
Liquid Crystal Display (LCD) Driver DUTY = 1/3 DATA LATCH: 1 = ON, 0 = OFF — FxB2 FxB1 FxB0 0 0 0 FPx OUTPUT 1FRAME VLCD VLCD1 VLCD2 VLCD3 — — — — — — — FxB2 FxB1 FxB0 0 0 1 FxB2 FxB1 FxB0 0 1 0 FxB2 FxB1 FxB0 1 0 0 FxB2 FxB1 FxB0 0 1 1 FxB2 FxB1 FxB0 1 1 0 FxB2 FxB1 FxB0 1 0 1 FxB2 FxB1 FxB0 1 1 1 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2
Liquid Crystal Display (LCD) Driver I/O Signals DUTY = 1/4 DATA LATCH: 1 = ON, 0 = OFF 1FRAME FxB3 FxB2 FxB1 FxB0 0 0 0 0 FPx OUTPUT VLCD VLCD1 VLCD2 VLCD3 FxB3 FxB2 FxB1 FxB0 0 0 0 1 FxB3 FxB2 FxB1 FxB0 0 0 1 0 FxB3 FxB2 FxB1 FxB0 0 0 1 1 FxB3 FxB2 FxB1 FxB0 0 1 0 0 FxB3 FxB2 FxB1 FxB0 0 1 0 1 FxB3 FxB2 FxB1 FxB0 0 1 1 0 FxB3 FxB2 FxB1 FxB0 0 1 1 1 Figure 17-10. 1/4 Duty LCD Frontplane Driver Waveforms MC68HC908LJ24/LK24 — Rev. 2.
Liquid Crystal Display (LCD) Driver DUTY = 1/4 DATA LATCH: 1 = ON, 0 = OFF 1FRAME FxB3 FxB2 FxB1 FxB0 1 0 0 0 FPx OUTPUT VLCD VLCD1 VLCD2 VLCD3 FxB3 FxB2 FxB1 FxB0 1 0 0 1 FxB3 FxB2 FxB1 FxB0 1 0 1 0 FxB3 FxB2 FxB1 FxB0 1 0 1 1 FxB3 FxB2 FxB1 FxB0 1 1 0 0 FxB3 FxB2 FxB1 FxB0 1 1 0 1 FxB3 FxB2 FxB1 FxB0 1 1 1 0 FxB3 FxB2 FxB1 FxB0 1 1 1 1 Figure 17-11.
Liquid Crystal Display (LCD) Driver Seven Segment Display Connection 17.8 Seven Segment Display Connection The following shows an example for connecting a 7-segment LCD display to the LCD driver. The example uses 1/3 duty cycle, with pins BP0, BP1, BP2, FP0, FP1, and FP2 connected as shown in Figure 17-12. The output waveforms are shown in Figure 17-13.
Liquid Crystal Display (LCD) Driver DUTY = 1/3 1FRAME VLCD VLCD1 VLCD2 BP0 VLCD3 F0B2 F0B1 F0B0 0 1 0 F1B2 F1B1 F1B0 0 1 0 F2B2 F2B1 F2B0 0 1 1 — — — BP1 VLCD VLCD1 VLCD2 VLCD3 BP2 VLCD VLCD1 VLCD2 VLCD3 FP0 VLCD VLCD1 VLCD2 VLCD3 FP1 VLCD VLCD1 VLCD2 VLCD3 FP2 VLCD VLCD1 VLCD2 VLCD3 Figure 17-13. BP0–BP2 and FP0–FP2 Output Waveforms for 7-Segment Display Example Data Sheet 366 MC68HC908LJ24/LK24 — Rev. 2.
Liquid Crystal Display (LCD) Driver Seven Segment Display Connection The voltage waveform across the "f" segment of the LCD (between BP1 and FP0) is illustrated in Figure 17-14. As shown in the waveform, the voltage peaks reach the LCD-ON voltage, VLCD, therefore, the segment will be ON. +VLCD +VLCD1 +VLCD2 BP1–FP0 0 –VLCD2 –VLCD1 –VLCD Figure 17-14. "f" Segment Voltage Waveform The voltage waveform across the "e" segment of the LCD (between BP2 and FP0) is illustrated in Figure 17-15.
Liquid Crystal Display (LCD) Driver 17.9 I/O Registers Nineteen (19) registers control LCD driver module operation: • LCD control register (LCDCR) • LCD clock register (LCDCLK) • LCD data registers (LDAT1–LDAT17) 17.9.
Liquid Crystal Display (LCD) Driver I/O Registers Table 17-2. Resistor Ladder Selection FC LC Action X 0 Each resistor is approximately 37 kΩ (default) 0 1 Each resistor is approximately 146 kΩ 1 1 Fast charge mode LCCON[3:0] — LCD Contrast Control These read/write bits select the bias voltage, Vbias. This voltage controls the contrast of the LCD. Maximum contrast is set when LCCON[3:0] =%0000; minimum contrast is set when LCCON[3:0] =%1111. Table 17-3.
Liquid Crystal Display (LCD) Driver 17.9.2 LCD Clock Register (LCDCLK) The LCD clock register (LCDCLK): • Selects the fast charge duty cycle • Selects LCD driver duty cycle • Selects LCD waveform base clock Address: $004F Bit 7 Read: 0 Write: Reset: 6 5 4 3 2 1 Bit 0 FCCTL1 FCCTL0 DUTY1 DUTY0 LCLK2 LCLK1 LCLK0 0 0 0 0 0 0 0 0 = Unimplemented Figure 17-17.
Liquid Crystal Display (LCD) Driver I/O Registers DUTY[1:0] — Duty Cycle Select These read/write bits select the duty cycle of the LCD driver output waveforms. The multiplexed FP0/BP3 pin is controlled by the duty cycle selected. Reset clears these bits. Table 17-5. LCD Duty Cycle Selection DUTY1:DUTY0 Description 00 Static selected; FP0/BP3 pin function as FP0. 01 1/3 duty cycle selected; FP0/BP3 pin functions as FP0. 10 1/4 duty cycle selected; FP0/BP3 pin functions as BP3.
Liquid Crystal Display (LCD) Driver 17.9.3 LCD Data Registers (LDAT1–LDAT17) The seventeen (17) LCD data registers enable and disable the drive to the corresponding LCD segments. Addr.
Liquid Crystal Display (LCD) Driver I/O Registers $005B $005C $005D $005E $005F $0060 $0061 $0062 Read: LCD Data Register 10 Write: (LDAT10) Reset: Read: LCD Data Register 11 Write: (LDAT11) Reset: Read: LCD Data Register 12 Write: (LDAT12) Reset: Read: LCD Data Register 13 Write: (LDAT13) Reset: Read: LCD Data Register 14 Write: (LDAT14) Reset: Read: LCD Data Register 15 Write: (LDAT15) Reset: Read: LCD Data Register 16 Write: (LDAT16) Reset: F19B3 F19B2 F19B1 F19B0 F18B3 F18B2 F18B1 F18B0
Liquid Crystal Display (LCD) Driver Data Sheet 374 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 18. Input/Output (I/O) Ports 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 18.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 18.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . 380 18.3.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . 381 18.4 Port B . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output (I/O) Ports 18.2 Introduction Forty-eight (48) bidirectional input-output (I/O) pins form six parallel ports. All I/O pins are programmable as inputs or outputs. NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. Addr.
Input/Output (I/O) Ports Introduction Addr.
Input/Output (I/O) Ports Table 18-1.
Input/Output (I/O) Ports Introduction Table 18-1.
Input/Output (I/O) Ports 18.3 Port A Port A is an 8-bit special function port that shares four of its port pins with the analog-to-digital converter (ADC) module and four of its port pins with the keyboard interrupt module (KBI). 18.3.1 Port A Data Register (PTA) The port A data register contains a data latch for each of the eight port A pins.
Input/Output (I/O) Ports Port A ADC[3:0] — ADC channels 0 to 3 ADC[3:0] are pins used for the input channels to the analog-to-digital converter module. The channel select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used as an ADC input and overrides any control from the port I/O logic. See Section 16. Analog-to-Digital Converter (ADC). NOTE: Care must be taken when reading port A while applying analog voltages to ADC[3:0] pins.
Input/Output (I/O) Ports READ DDRA ($0004) INTERNAL DATA BUS WRITE DDRA ($0004) RESET DDRAx WRITE PTA ($0000) PTAx PTAx READ PTA ($0000) Figure 18-4. Port A I/O Circuit When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 18-2 summarizes the operation of the port A pins. Table 18-2.
Input/Output (I/O) Ports Port B 18.4 Port B Port B is a 8-bit special function port that shares two of its port pins with the infrared serial communication interface (IRSCI) module, two of its port pins with the timer interface module 1 (TIM1) module, two of its port pins with the timer interface module 2 (TIM2), and two of its port pins with the ADC module. Port pins PTB0–PTB5 can be configured for direct LED drive. 18.4.
Input/Output (I/O) Ports T1CH[1:0] — Timer 1 Channel I/O Bits The T1CH1 and T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTB2/T1CH0 and PTB3/T1CH1 pins are timer channel I/O pins or general-purpose I/O pins. See Section 11. Timer Interface Module (TIM). T2CH[1:0] — Timer 2 Channel I/O Bits The T2CH1 and T2CH0 pins are the TIM1 input capture/output compare pins.
Input/Output (I/O) Ports Port B 18.4.2 Data Direction Register B (DDRB) Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $0005 Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Figure 18-6.
Input/Output (I/O) Ports Table 18-3 summarizes the operation of the port B pins. Table 18-3. Port B Pin Functions Accesses to DDRB DDRB Bit PTB Bit 0 X(1) 1 X Accesses to PTB I/O Pin Mode Read/Write Read Write Input, Hi-Z(2) DDRB[7:0] Pin PTB[7:0](3) Output DDRB[7:0] PTB[7:0] PTB[7:0] Notes: 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. 18.4.
Input/Output (I/O) Ports Port C 18.5 Port C Port C is an 8-bit special function port that shares all of its port pins with the liquid crystal display (LCD) driver module. Port pins PTC0–PTC7 can be configured for direct LED drive. 18.5.1 Port C Data Register (PTC) The port C data register contains a data latch for each of the eight port C pins.
Input/Output (I/O) Ports 18.5.2 Data Direction Register C (DDRC) Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $0006 Bit 7 6 5 4 3 2 1 Bit 0 DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 0 Figure 18-10.
Input/Output (I/O) Ports Port C When DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 18-4 summarizes the operation of the port C pins. Table 18-4.
Input/Output (I/O) Ports 18.6 Port D Port D is an 8-bit special function port that shares its pins with the serial peripheral interface (SPI) module, keyboard interrupt module, RTC module, MMIIC module, and timer modules. 18.6.1 Port D Data Register (PTD) The port D data register contains a data latch for each of the eight port D pins.
Input/Output (I/O) Ports Port D SDA, SCL — Multi-Master IIC Data and Clock Pins The SDA and SCL pins are multi-master IIC data and clock opendrain pins, enabled by setting the MMEN bit in the MMIIC control register (MMCR). Port pins used as MMIIC will override any control from the port I/O logic. See Section 15. Multi-Master IIC Interface (MMIIC).
Input/Output (I/O) Ports 18.6.2 Data Direction Register D (DDRD) Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $0007 Bit 7 6 5 4 3 2 1 Bit 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Figure 18-14.
Input/Output (I/O) Ports Port D When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 18-5 summarizes the operation of the port D pins. Table 18-5.
Input/Output (I/O) Ports 18.7 Port E Port E is an 8-bit special function port that shares all of its port pins with the liquid crystal display (LCD) driver module. Port pins PTE0–PTE7 can be configured for direct LED drive. 18.7.1 Port E Data Register (PTE) The port E data register contains a data latch for each of the eight port E pins.
Input/Output (I/O) Ports Port E 18.7.2 Data Direction Register E (DDRE) Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $0009 Bit 7 6 5 4 3 2 1 Bit 0 DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 0 0 0 0 0 0 0 0 Figure 18-17.
Input/Output (I/O) Ports When DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 18-6 summarizes the operation of the port E pins. Table 18-6.
Input/Output (I/O) Ports Port F 18.8 Port F Port F is an 8-bit general-purpose I/O port. Port pins PTF0–PTF7 can be configured for direct LED drive. NOTE: PTF0–PTF7 are not available in the 64-pin packages. 18.8.1 Port F Data Register (PTF) The port F data register contains a data latch for each of the eight port F pins.
Input/Output (I/O) Ports 18.8.2 Data Direction Register F (DDRF) Data direction register F determines whether each port F pin is an input or an output. Writing a logic 1 to a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the output buffer. NOTE: For those devices packaged in a 64-pin package, PTF0–PTF7 are connected to ground internally. DDRF0–DDRF7 should be set to a 0 to configure PTF0–PTF7 as inputs.
Input/Output (I/O) Ports Port F When DDRFx is a logic 1, reading address $000A reads the PTFx data latch. When DDRFx is a logic 0, reading address $000A reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 18-7 summarizes the operation of the port F pins. Table 18-7.
Input/Output (I/O) Ports Data Sheet 400 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 19. External Interrupt (IRQ) 19.1 Contents 19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402 19.4.1 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 19.
External Interrupt (IRQ) 19.4 Functional Description A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 19-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: • Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch.
External Interrupt (IRQ) Functional Description RESET ACK TO CPU FOR BIL/BIH INSTRUCTIONS INTERNAL ADDRESS BUS VECTOR FETCH DECODER VDD VDD INTERNAL PULLUP DEVICE IRQF D CLR Q IRQ IRQ INTERRUPT REQUEST SYNCHRONIZER CK IMASK MODE TO MODE SELECT LOGIC HIGH VOLTAGE DETECT Figure 19-1. IRQ Module Block Diagram Addr.
External Interrupt (IRQ) 19.4.1 IRQ Pin A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and lowlevel-sensitive. With MODE set, both of the following actions must occur to clear IRQ: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch.
External Interrupt (IRQ) IRQ Module During Break Interrupts 19.5 IRQ Module During Break Interrupts The system integration module (SIM) controls whether the IRQ latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. (See Section 23. Break Module (BRK).) To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit.
External Interrupt (IRQ) Address: Read: $001E Bit 7 6 5 4 3 2 0 0 0 0 IRQF 0 Write: Reset: ACK 0 0 0 0 0 0 1 Bit 0 IMASK MODE 0 0 = Unimplemented Figure 19-3. IRQ Status and Control Register (INTSCR) IRQF — IRQ Flag Bit This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK — IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always reads as logic 0.
Data Sheet — MC68HC908LJ24 Section 20. Keyboard Interrupt Module (KBI) 20.1 Contents 20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 20.4 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409 20.5.
Keyboard Interrupt Module (KBI) 20.3 Features Features of the keyboard interrupt module include the following: • Eight keyboard interrupt pins with pullup devices • Separate keyboard interrupt enable bits and one keyboard interrupt mask • Programmable edge-only or edge- and level- interrupt sensitivity • Exit from low-lower modes Addr.
Keyboard Interrupt Module (KBI) Functional Description 20.5 Functional Description INTERNAL BUS KBI0 ACKK VDD . KBIE0 TO PULLUP ENABLE D . CLR VECTOR FETCH DECODER KEYF RESET Q SYNCHRONIZER CK . KEYBOARD INTERRUPT FF KBI7 KEYBOARD INTERRUPT REQUEST IMASKK MODEK KBIE7 TO PULLUP ENABLE Figure 20-2. Keyboard Interrupt Block Diagram Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register independently enables or disables a port A or port D pin as a keyboard interrupt pin.
Keyboard Interrupt Module (KBI) If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register KBSCR.
Keyboard Interrupt Module (KBI) Functional Description NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. 20.5.1 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore a false interrupt can occur as soon as the pin is enabled.
Keyboard Interrupt Module (KBI) 20.6 Keyboard Interrupt Registers Two registers control the operation of the keyboard interrupt module: • Keyboard status and control register (KBSCR) • Keyboard interrupt enable register (KBIER) 20.6.
Keyboard Interrupt Module (KBI) Keyboard Interrupt Registers IMASKK — Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK.
Keyboard Interrupt Module (KBI) 20.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 20.7.1 Wait Mode The keyboard interrupt module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 20.7.2 Stop Mode The keyboard interrupt module remains active in stop mode.
Data Sheet — MC68HC908LJ24 Section 21. Computer Operating Properly (COP) 21.1 Contents 21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 21.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416 21.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 21.4.1 ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 21.4.2 STOP Instruction . . .
Computer Operating Properly (COP) 21.3 Functional Description Figure 21-1 shows the structure of the COP module. RESET STATUS REGISTER COP TIMEOUT CLEAR STAGES 5–12 STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH RESET CIRCUIT 12-BIT COP PRESCALER CLEAR ALL STAGES ICLK COPCTL WRITE COP CLOCK 6-BIT COP COUNTER COPEN (FROM SIM) COP DISABLE (COPD FROM CONFIG1) RESET COPCTL WRITE CLEAR COP COUNTER COP RATE SEL (COPRS FROM CONFIG1) Figure 21-1.
Computer Operating Properly (COP) I/O Signals A COP reset pulls the RST pin low for 32 ICLK cycles and sets the COP bit in the SIM reset status register (SRSR). In monitor mode, the COP is disabled if the RST pin or the IRQ is held at VTST. During the break state, VTST on the RST pin disables the COP. NOTE: Place COP clearing instructions in the main program and not in an interrupt subroutine.
Computer Operating Properly (COP) 21.4.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. 21.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 21.4.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the CONFIG1 register. (See Figure 21-2 and Section 5. Configuration Registers (CONFIG).) 21.4.
Computer Operating Properly (COP) COP Control Register 21.5 COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Address: $FFFF Bit 7 6 5 4 3 Read: Low byte of reset vector Write: Clear COP counter Reset: Unaffected by reset 2 1 Bit 0 Figure 21-3. COP Control Register (COPCTL) 21.
Computer Operating Properly (COP) 21.8.1 Wait Mode The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. 21.8.2 Stop Mode Stop mode turns off the ICLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode.
Data Sheet — MC68HC908LJ24 Section 22. Low-Voltage Inhibit (LVI) 22.1 Contents 22.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 22.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 22.4.2 Forced Reset Operation . . . . . . . .
Low-Voltage Inhibit (LVI) Addr. Register Name Bit 7 6 Read: LVIOUT Low-Voltage Inhibit Status $FE0F Register Write: (LVISR) Reset: 0 LVIIE 5 4 3 2 1 Bit 0 LVIIF 0 0 0 0 0 0 0 0 0 LVIIACK 0 0 0 = Unimplemented Figure 22-1. LVI I/O Register Summary 22.4 Functional Description Figure 22-2 shows the structure of the LVI module.
Low-Voltage Inhibit (LVI) Functional Description The LVI trip point selection bits, LVISEL[1:0], select the trip point voltage, VTRIPF, to be configured for 5V or 3V operation. The actual trip points are shown in Section 24. Electrical Specifications. Setting LVI interrupt enable bit, LVIIE, enables LVI interrupts whenever the LVIOUT bit toggles (from logic 0 to logic 1, or from logic 1 to logic 0). NOTE: After a power-on reset (POR) the LVI’s default mode of operation is 3V.
Low-Voltage Inhibit (LVI) 22.4.1 Polled LVI Operation In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling the LVIOUT bit, or by setting the LVI interrupt enable bit, LVIIE, to enable interrupt requests. In the configuration register 1 (CONFIG1), the LVIPWRD bit must be at logic 0 to enable the LVI module, and the LVIRSTD bit must be at logic 1 to disable LVI resets. The LVI interrupt flag, LVIIF, is set whenever the LVIOUT bit changes state (toggles).
Low-Voltage Inhibit (LVI) LVI Status Register 22.4.4 LVI Trip Selection The trip point selection bits, LVISEL[1:0], in the CONFIG2 register select whether the LVI is configured for 5V or 3 V operation. (See Section 5. Configuration Registers (CONFIG).) NOTE: The MCU is guaranteed to operate at a minimum supply voltage. The trip point (VTRIPF [5V] or VTRIPF [3V]) may be lower than this. (See Section 24. Electrical Specifications for the actual trip point voltages.) 22.
Low-Voltage Inhibit (LVI) LVIIE — LVI Interrupt Enable Bit This read/write bit enables the LVIIF bit to generate CPU interrupt requests. Reset clears the LVIIE bit. 1 = LVIIF can generate CPU interrupt requests 0 = LVIIF cannot generate CPU interrupt requests LVIIF — LVI Interrupt Flag This clearable, read-only flag is set whenever the LVIOUT bit toggles. Reset clears the LVIIF bit.
Data Sheet — MC68HC908LJ24 Section 23. Break Module (BRK) 23.1 Contents 23.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 23.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428 23.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 430 23.4.2 CPU During Break Interrupts . . . . . . . . . . . . . .
Break Module (BRK) 23.3 Features Features of the break module include: • Accessible input/output (I/O) registers during the break interrupt • CPU-generated break interrupts • Software-generated break interrupts • COP disabling during break interrupts 23.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the CPU.
Break Module (BRK) Functional Description IAB15–IAB8 BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB15–IAB0 BREAK CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB7–IAB0 Figure 23-1. Break Module Block Diagram Addr.
Break Module (BRK) 23.4.1 Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. 23.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress.
Break Module (BRK) Break Module Registers 23.5.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. 23.6 Break Module Registers These registers control and monitor operation of the break module: • Break status and control register (BRKSCR) • Break address register high (BRKH) • Break address register low (BRKL) • SIM break status register (SBSR) • SIM break flag control register (SBFCR) 23.6.
Break Module (BRK) BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = (When read) Break address match 0 = (When read) No break address match 23.6.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address.
Break Module (BRK) Break Module Registers Address: Read: Write: Reset: $FE00 Bit 7 6 5 4 3 2 R R R R R R 0 0 0 0 0 0 R = Reserved Note: Writing a logic 0 clears SBSW. 1 SBSW Note 0 Bit 0 R 0 Figure 23-6. SIM Break Status Register (SBSR) SBSW — Break Wait Bit This status bit is set when a break interrupt causes an exit from wait mode or stop mode. Clear SBSW by writing a logic 0 to it. Reset clears SBSW.
Break Module (BRK) 23.6.4 SIM Break Flag Control Register The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: Read: Write: Reset: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 23-7.
Data Sheet — MC68HC908LJ24 Section 24. Electrical Specifications 24.1 Contents 24.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 24.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 436 24.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 437 24.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 24.6 5V DC Electrical Characteristics . . . . . . . . . .
Electrical Specifications 24.3 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to DC Electrical Characteristics for guaranteed operating conditions. Table 24-1. Absolute Maximum Ratings Characteristic(1) Symbol Value Unit Supply voltage VDD –0.3 to +6.0 V Input voltage All pins (except IRQ) IRQ pin VIN VSS – 0.3 to VDD + 0.
Electrical Specifications Functional Operating Range 24.4 Functional Operating Range Table 24-2. Functional Operating Range Characteristic Operating temperature range Operating voltage range Symbol Value Unit TA – 40 to +85 °C VDD 3.3 ± 10% 5 ± 10% V 24.5 Thermal Characteristics Table 24-3.
Electrical Specifications 24.6 5V DC Electrical Characteristics Table 24-4. 5V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (ILOAD = –2.0 mA) All ports VOH VDD –0.8 — — V Output low voltage (ILOAD = 1.6mA) All ports (ILOAD = 15.0 mA) PTB0–PTB5, PTC0–PTC7, PTE0–PTE7, PTF0–PTF7 VOL — — 0.4 V Input high voltage All ports, RST, IRQ, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, RST, IRQ, OSC1 VIL VSS — 0.
Electrical Specifications 3.3V DC Electrical Characteristics Notes: 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only. 3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. 4.
Electrical Specifications Table 24-5. 3.3V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit Capacitance Ports (as input or output) COUT CIN — — — — 12 8 pF POR re-arm voltage(7) VPOR 0 — 100 mV POR rise-time ramp rate(8) RPOR 0.02 — — V/ms VHI 1.5 × VDD — 8 V RPU1 RPU2 21 21 30 30 39 39 kΩ kΩ Low-voltage inhibit, trip falling voltage VTRIPF 2.1 — 2.8 V Low-voltage inhibit, trip rising voltage VTRIPR 2.2 — 2.
Electrical Specifications 3.3V Control Timing 24.9 3.3V Control Timing Table 24-7. 3.3V Control Timing Characteristic(1) Symbol Min Max Unit Internal operating frequency(2) fOP — 4 MHz RST input pulse width low(3) tIRL 1.5 — µs Notes: 1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3.
Electrical Specifications 24.11 3.3V Oscillator Characteristics Table 24-9. 3.3V Oscillator Specifications Characteristic Symbol Min Typ Max 47k(1) Unit Internal oscillator clock frequency fICLK External reference clock to OSC1(2) fOSC dc — 16M Hz Crystal reference frequency(3) fXCLK — 32.768k 4.
Electrical Specifications 5V ADC Electrical Characteristics 24.12 5V ADC Electrical Characteristics Table 24-10. 5V ADC Electrical Characteristics Characteristic Symbol Min Max Unit Notes Supply voltage VDDA 4.5 5.5 V VDDA is an dedicated pin and should be tied to VDD on the PCB with proper decoupling. Input range VADIN 0 VDDA V VADIN ≤ VDDA Resolution BAD 10 10 bits Absolute accuracy AAD — ± 1.
Electrical Specifications 24.13 3.3V ADC Electrical Characteristics Table 24-11. 3.3V ADC Electrical Characteristics Characteristic Symbol Min Max Unit Notes Supply voltage VDDA 3.0 3.6 V VDDA is an dedicated pin and should be tied to VDD on the PCB with proper decoupling. Input range VADIN 0 VDDA V VADIN ≤ VDDA Resolution BAD 10 10 bits Absolute accuracy AAD — ± 1.
Electrical Specifications Timer Interface Module Characteristics 24.14 Timer Interface Module Characteristics Table 24-12. Timer Interface Module Characteristics Characteristic Input capture pulse width Symbol Min Max Unit tTIH, tTIL 1 — tCYC 24.15 CGM Electrical Specifications Table 24-13. CGM Electrical Specifications Characteristic Symbol Min Typ Max Unit Reference frequency fRDV 30 32.768 100 kHz Range nominal multiplies fNOM — 38.
Electrical Specifications 24.16 5V SPI Characteristics Table 24-14.
Electrical Specifications 3.3V SPI Characteristics 24.17 3.3V SPI Characteristics Table 24-15. 3.
Electrical Specifications SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE SPSCK OUTPUT CPOL = 1 NOTE 5 4 5 4 6 MISO INPUT MSB IN BITS 6–1 11 MOSI OUTPUT MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
Electrical Specifications 3.
Electrical Specifications 24.18 FLASH Memory Characteristics Table 24-16. FLASH Memory Electrical Characteristics Characteristic RAM data retention voltage Symbol Min. Max. Unit VRDR 1.
Data Sheet — MC68HC908LJ24 Section 25. Mechanical Specifications 25.1 Contents 25.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 25.3 64-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . 452 25.4 64-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . 453 25.5 80-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . 454 25.6 80-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Specifications 25.3 64-Pin Low-Profile Quad Flat Pack (LQFP) 4X 4X 16 TIPS 0.2 H A–B D 0.2 C A–B D A2 0.05 S 49 64 (S) 1 48 θ1 A 0.25 B θ E E1 E1/2 VIEW Y 16 E/2 VIEW AA NOTES: 1. ALL DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 5.
Mechanical Specifications 64-Pin Quad Flat Pack (QFP) 25.4 64-Pin Quad Flat Pack (QFP) L 48 33 DETAIL A S D S V P B M C A–B S 0.20 (0.008) M B B 0.20 (0.008) L 0.05 (0.002) A–B –B– S –A– D 32 H A–B 49 –A–, –B–, –D– DETAIL A 64 17 F 1 16 –D– A 0.20 (0.008) H A–B S D S 0.05 (0.002) A–B S 0.20 (0.008) M C A–B S D S M N J M C M H 0.20 (0.008) DATUM PLANE M C A–B S D S SECTION B–B VIEW ROTATED 90° 0.10 (0.
Mechanical Specifications 25.5 80-Pin Low-Profile Quad Flat Pack (LQFP) B D B D/2 D1 D1/2 PIN 1 IDEx 80 VIEW Y e/2 61 1 X 60 X=A, B, or D VIEW Y 3 PLACES E/2 b1 E c PLATING c1 E1 A B E1/2 20 41 21 SECTION B–B 0.200 H A–B D 4X 0.200 C A–B D A2 8X θ2 VIEW P H 0.1 C A A1 76X BASE METAL 80 PLACES ROTATED 90° CLOCKWISE 40 D 4X b 0.08 M C A–B D e C SEATING PLANE S θ1 R (R1) R (R2) GAGE PLANE θ (L2) 0.25 L (L1) NOTES: 1.
Mechanical Specifications 80-Pin Quad Flat Pack (QFP) 25.6 80-Pin Quad Flat Pack (QFP) L 41 60 61 D S P B M –A–,–B–,–D– 0.20 V B C A–B D S 0.20 M B H A–B L 0.05 D –B– –A– S S 40 DETAIL A DEATIL A 21 80 1 0.20 A H A–B M S F 20 –D– D S 0.05 A–B J S 0.20 C A–B M S D S D M E DETAIL C C –H– DATUM PLANE 0.20 M C A–B S D S SECTION B–B VIEW ROTATED 90° 0.10 –C– SEATING PLANE N H M G U T DATUM PLANE –H– R K W X DETAIL C Q NOTES: 1.
Mechanical Specifications Data Sheet 456 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Section 26. Ordering Information 26.1 Contents 26.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 26.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 26.2 Introduction This section contains ordering numbers for the MC68HC908LJ24. 26.3 MC Order Numbers Table 26-1.
Ordering Information Data Sheet 458 MC68HC908LJ24/LK24 — Rev. 2.
Data Sheet — MC68HC908LJ24 Appendix A. MC68HC908LK24 A.1 Contents A.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 A.3 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .460 A.4 Low-Voltage Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 A.5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 A.5.1 5V DC Electrical Characteristics . . . . . . . .
A.3 Oscillator The low-power oscillator supports a reference frequency of 32.768kHz only; either from a crystal oscillator circuit (Figure A-1) or a direct clock input to the OSC1 pin. MCU OSC1 OSC2 RB RS 32.768kHz C1 X1 C2 Figure A-1. MC68HC908LK24 Crystal Oscillator Connection A.4 Low-Voltage Inhibit The LVIPWRD bit in CONFIG1 register is logic 1 after any reset.
A.5 Electrical Specifications Electrical specifications for the MC68HC908LJ24 apply to the MC68HC908LK24, except for the parameters indicated below. A.5.1 5V DC Electrical Characteristics Table A-1. 5V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit — 5.5 7.5 µA 3.7 3.62 — — 4.7 4.
A.5.3 5V Oscillator Characteristics Table A-3. 5V Oscillator Specifications Characteristic Symbol Min Typ Max Unit External reference clock to OSC1(1) fOSC dc 32.768k — Hz Crystal reference frequency(2) fXCLK — 32.768k — Hz Notes: 1. No more than 10% duty cycle deviation from 50%. 2. Fundamental mode crystals only. A.5.4 3.3V Oscillator Characteristics Table A-4. 3.3V Oscillator Specifications Characteristic Symbol Min Typ Max Unit External reference clock to OSC1(1) fOSC dc 32.
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