Datasheet

Clock Generator Module (CGM)
I/O Signals
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Clock Generator Module (CGM) 123
8.4.9 CGM External Connections
In its typical configuration, the CGM requires up to four external
components.
Figure 8-3 shows the external components for the PLL:
• Bypass capacitor, C
BYP
• Filter network
Care should be taken with PCB routing in order to minimize signal cross
talk and noise. (See 8.9 Acquisition/Lock Time Specifications for
routing information, filter network and its effects on PLL performance.)
Figure 8-3. CGM External Connections
8.5 I/O Signals
The following paragraphs describe the CGM I/O signals.
C
BYP
Note: Filter network in box can be replaced with a 0.47µF capacitor, but will degrade stability.
10 kΩ
0.01 µF
0.033 µF
0.1 µF
V
SSA
V
DDA
CGMXFC
V
DD
MCU