Datasheet

Real Time Clock (RTC)
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
226 Real Time Clock (RTC) Freescale Semiconductor
A negative E-value indicates the number of CGMXCLK cycles that
needs to be subtracted, because the CGMXCLK is slower than the ideal
32.768kHz; 32768 CGMXCLK cycles will be more longer than 1-second.
A positive E-value indicates the number of CGMXCLK cycles that needs
to be added, because the CGMXCLK is faster than the ideal 32.768kHz;
32768 CGMXCLK cycles will be more shorter than 1-second.
If the time difference is more than 31 CGMXCLK cycles, the E-register
will overflow, causing the EVOL flag to be set. The maximum (+30) or
minimum (–30) value will remain in the E-register.
After calibration, with the E-value stored in the calibration data register,
clock compensation is only enabled when the COMEN bit is set in
RTCCR2. As the E-value is the time difference for 15 seconds, the
CGMXCLK is modified for every 15-second intervals. The CGMXCLK
additions and subtractions are simulated using programmable dividers,
therefore, the compensated clock does not have the same period within
the 15-second, but is consistent for every 15-second periods. See Table
12-2 and Figure 12-4.
12.7.1 Calibration Error
During clock calibration, the reference signal to the CALIN pin is not
synchronized to the CGMXCLK being measured. A maximum
inaccuracy of minus 1.5×CGMXCLK period or plus 1×CGMXCLK period
will be introduced to the time difference measured.
Table 12-2. Compensation Algorithm for Different Values of E
Period A Period B
E
Number of
CGMXCLK Cycles
CGMXCLK
Divider A
Number of
CGMXCLK Cycles
CGMXCLK
Divider B
–30 ≤ E ≤ –16 (|E| – 15) × 32766 32766 (30 – |E|) × 32767 32767
–15 ≤ E ≤ –1 |E| × 32767 32767 (15 – |E|) × 32768 32768
E = 0 No compensation is required: Divider is 32768 throughout.
1 ≤ E ≤ 15 |E| × 32769 32769 (15 – |E|) × 32768 32769
16 ≤ E ≤ 30 (|E| – 15) × 32770 32770 (30 – |E|) × 32769 32769