Datasheet

Real Time Clock (RTC)
RTC Registers
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Real Time Clock (RTC) 235
SECIE — Second Interrupt Enable
This read/write bit enables the second flag, SECF, to generate CPU
interrupt requests. Reset clears the SECIE bit.
1 = SECF enabled to generate CPU interrupt
0 = SECF not enabled to generate CPU interrupt
TB1IE — Timebase 1 Interrupt Enable
This read/write bit enables the timebase1 flag, TB1F, to generate
CPU interrupt requests. Reset clears the TB1IE bit.
1 = TB1F enabled to generate CPU interrupt
0 = TB1F not enabled to generate CPU interrupt
TB2IE — Timebase 2 Interrupt Enable
This read/write bit enables the timebase2 flag, TB2F, to generate
CPU interrupt requests. Reset clears the TB2IE bit.
1 = TB2F enabled to generate CPU interrupt
0 = TB2F not enabled to generate CPU interrupt
12.10.4 RTC Control Register 2 (RTCCR2)
The RTC control register 2 (RTCCR2) contains control and clock
selection bits for RTC operation.
COMEN — RTC Compensation Enable
This read/write bit enables the clock compensation mechanism for
CGMXCLK frequency errors. Reset has no effect on COMEN bit.
1 = Compensation mechanism enabled
0 = Compensation mechanism not enabled
Address: $0043
Read:
COMEN*
0
CHRE RTCE* TBH
000
Write: CHRCLR
Reset: U 0 0 0
††
0000
= Unimplemented
†† Reset by POR only.
* COMEN and RTCE bits are write-protected; unprotect by a write sequence to RTCWE[1:0] in RTCCOMR.
Figure 12-9. RTC Control Register 2 (RTCCR2)