Datasheet

List of Figures
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor List of Figures 29
Figure Title Page
14-10 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . .302
14-11 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . .305
14-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
14-13 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . .312
14-14 SPI Status and Control Register (SPSCR). . . . . . . . . . . . . . .314
14-15 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .317
15-1 MMIIC I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .321
15-2 Multi-Master IIC Address Register (MMADR). . . . . . . . . . . . .321
15-3 Multi-Master IIC Control Register (MMCR). . . . . . . . . . . . . . .323
15-4 Multi-Master IIC Master Control Register (MIMCR) . . . . . . . .324
15-5 Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . . .326
15-6 Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . . .328
15-7 Multi-Master IIC Data Receive Register (MMDRR) . . . . . . . .329
15-8 Data Transfer Sequences for Master/Slave
Transmit/Receive Modes. . . . . . . . . . . . . . . . . . . . . . . . . .331
16-1 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .335
16-2 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
16-3 8-Bit Truncation Mode Error . . . . . . . . . . . . . . . . . . . . . . . . . .339
16-4 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .342
16-5 ADRH and ADRL in 8-Bit Truncated Mode. . . . . . . . . . . . . . .344
16-6 ADRH and ADRL in Right Justified Mode. . . . . . . . . . . . . . . .344
16-7 ADRH and ADRL in Left Justified Mode. . . . . . . . . . . . . . . . .345
16-8 ADRH and ADRL in Left Justified Sign Data Mode . . . . . . . .345
16-9 ADC Clock Control Register (ADCLK) . . . . . . . . . . . . . . . . . .346
17-1 LCD I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .351
17-2 LCD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
17-3 Simplified LCD Schematic (1/3 Duty, 1/3 Bias) . . . . . . . . . . .354
17-4 Fast Charge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
17-5 Static LCD Backplane Driver Waveform. . . . . . . . . . . . . . . . .359
17-6 1/3 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . .359
17-7 1/4 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . .360
17-8 Static LCD Frontplane Driver Waveforms. . . . . . . . . . . . . . . .361
17-9 1/3 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . .362
17-10 1/4 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . .363