Datasheet

Multi-Master IIC Interface (MMIIC)
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
320 Multi-Master IIC Interface (MMIIC) Freescale Semiconductor
This Multi-master IIC module uses the SCL clock line and the SDA data
line to communicate with external DDC host or IIC interface. These two
pins are shared with port pins PTD6/KBI6 and PTD7/KBI7 respectively.
The outputs of SCL and SDA pins are open-drain type — no clamping
diode is connected between the pin and internal V
DD
. The maximum
data rate typically is 750k-bps. The maximum communication length and
the number of devices that can be connected are limited by a maximum
bus capacitance of 400pF.
15.3 Features
• Compatibility with multi-master IIC bus standard
• Software controllable acknowledge bit generation
• Interrupt driven byte by byte data transfer
• Calling address identification interrupt
• Auto detection of R/W bit and switching of transmit or receive
mode
• Detection of START, repeated START, and STOP signals
• Auto generation of START and STOP condition in master mode
• Arbitration loss detection and No-ACK awareness in master mode
• 8 selectable baud rate master clocks
• Automatic recognition of the received acknowledge bit
15.4 I/O Pins
The MMIIC module uses two I/O pins, shared with standard port I/O pins.
The full name of the MMIIC I/O pins are listed in Table 15-1. The generic
pin name appear in the text that follows.
Table 15-1. Pin Name Conventions
MMIIC
Generic Pin Names:
Full MCU Pin Names:
Pin Selected for
IIC Function By:
SDA PTD7/KBI7/SDA
(1)
MMEN bit in MMCR ($006C)
SCL PTD6/KBI6/SCL
(1)
MMEN bit in MMCR ($006C)
Notes:
1. Do not enable the MMIIC function if the pin is used for KBI.