Datasheet

Multi-Master IIC Interface (MMIIC)
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
326 Multi-Master IIC Interface (MMIIC) Freescale Semiconductor
15.5.4 Multi-Master IIC Status Register (MMSR)
MMRXIF — Multi-Master IIC Receive Interrupt Flag
This flag is set after the data receive register (MMDRR) is loaded with
a new received data. Once the MMDRR is loaded with received data,
no more received data can be loaded to the MMDRR register until the
CPU reads the data from the MMDRR to clear MMRXBF flag.
MMRXIF generates an interrupt request to CPU if the MMIEN bit in
MMCR is also set. This bit is cleared by writing "0" to it or by reset; or
when the MMEN = 0.
1 = New data in data receive register (MMDRR)
0 = No data received
Table 15-2. Baud Rate Select
MMBR2 MMBR1 MMBR0 Baud Rate
0 0 0 Internal bus clock ÷ 8
0 0 1 Internal bus clock ÷ 16
0 1 0 Internal bus clock ÷ 32
0 1 1 Internal bus clock ÷ 64
1 0 0 Internal bus clock ÷ 128
1 0 1 Internal bus clock ÷ 256
1 1 0 Internal bus clock ÷ 512
1 1 1 Internal bus clock ÷ 1024
Address: $006D
Bit 7654321Bit 0
Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK 0 MMTXBE MMRXBF
Write: 0 0
Reset:00001010
= Unimplemented
Figure 15-5. Multi-Master IIC Status Register (MMSR)