Datasheet

Liquid Crystal Display (LCD) Driver
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
370 Liquid Crystal Display (LCD) Driver Freescale Semiconductor
17.9.2 LCD Clock Register (LCDCLK)
The LCD clock register (LCDCLK):
• Selects the fast charge duty cycle
• Selects LCD driver duty cycle
• Selects LCD waveform base clock
FCCTL[1:0] — Fast Charge Duty Cycle Select
These read/write bits select the duty cycle of the fast charge duration.
Reset clears these bits. (See 17.5.4 Fast Charge and Low Current)
Address: $004F
Bit 7654321Bit 0
Read: 0
FCCTL1 FCCTL0 DUTY1 DUTY0 LCLK2 LCLK1 LCLK0
Write:
Reset:00000000
= Unimplemented
Figure 17-17. LCD Clock Register (LCDCLK)
Table 17-4. Fast Charge Duty Cycle Selection
FCCTL1:FCCTL0 Fast Charge Duty Cycle
00
In each LCDCLK/2 period, each bias resistor is reduced to
37 kΩ for a duration of LCDCLK/32.
01
In each LCDCLK/2 period, each bias resistor is reduced to
37 kΩ for a duration of LCDCLK/64.
10
In each LCDCLK/2 period, each bias resistor is reduced to
37 kΩ for a duration of LCDCLK/128.
11 Not used