Datasheet

Input/Output (I/O) Ports
Introduction
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Input/Output (I/O) Ports 379
D
(1)
0 DDRD0
SPI
RTC
SPCR ($0010) SPE
PTD0/SS/CALIN
RTCCOMR ($0040) CAL
1 DDRD1
SPCR ($0010) SPE
PTD1/MISO
2 DDRD2 PTD2/MOSI
3 DDRD3
SPCR ($0010) SPE
PTD3/SPSCK/CALOUT
RTCCOMR ($0040) CAL
4 DDRD4
KBI
TIM
KBIER ($001C) KBIE4
PTD4/KBI4/T1CLK
T1SC ($0020) PS[2:0]
5 DDRD5
KBIER ($001C) KBIE5
PTD5/KBI5/T2CLK
T2SC ($002B) PS[2:0]
6 DDRD6
KBI
MMIIC
KBIER ($001C) KBIE6
PTD6/KBI6/SCL
MMCR ($006C) MMEN
7 DDRD7
KBIER ($001C) KBIE7
PTD7/KBI7/SDA
MMCR ($006C) MMEN
E
0 DDRE0
LCD CONFIG2 ($001D) PEE
PTE0/FP11
1 DDRE1 PTE1/FP12
2 DDRE2 PTE2/FP13
3 DDRE3 PTE3/FP14
4 DDRE4 PTE4/FP15
5 DDRE5 PTE5/FP16
6 DDRE6 PTE6/FP17
7 DDRE7 PTE7/FP18
F
0 DDRF0
———
PTF0
1 DDRF1 PTF1
2 DDRF2 PTF2
3 DDRF3 PTF3
4 DDRF4 PTF4
5 DDRF5 PTF5
6 DDRF6 PTF6
7 DDRF7 PTF7
Notes:
1. In addition to the standard I/O function on PTD0 and PTD3–PTD7 pins, these pins are shared with two other modules.
For each of the pins, ONLY enable ONE module at any one time to avoid pin contention.
Table 18-1. Port Control Register Bits Summary (Sheet 2 of 2)
Port Bit DDR
Module Control
Pin
Module Register Control Bit